SLUSFF6 April 2025 LMG1020-Q1
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The layout of the LMG1020-Q1 is critical to its performance and functionality. The LMG1020-Q1 is available in a WCSP ball-grid array package, which enables low-inductance connection to a BGA-type GaN FET. Figure 7-10 shows the recommended layout of the LMG1020-Q1 with a ball-grid array GaN FET. Figure 7-11 presents a layout of LMG1020-Q1 with a 0.1μF feed-through capacitor and a larger 1μF capacitor.
A four-layer or higher layer count board is required to reduce the parasitic inductances of the layout to achieve suitable performance. To minimize inductance and board space, resistors and capacitors in the 0201 package are used here. The gate drive power loss must be calculated to ensure an 0201 resistor will be able to handle the power level.