The SPI controller has the option to set TXE8124 to be in a fail-safe state by programing the Fail-safe Enable Register to enable this feature and change the functionality of the pin from reset to fail-safe.

This register can get cleared during a POR event or other fault scenarios. The SPI controller has to rewrite this register every time if there is a fault scenario which will generate an interrupt to the SPI controller. After the interrupt is generated, the SPI controller can read the Fault Status Register to understand the source of the interrupt.

The bit 0 in Fail-safe Enable Register must be 1 to configure TXE8124 to be fail-safe mode.

Two Device Configuration Registers have to be written to program I/O configuration to ensure redundancy. If either of these registers get corrupted, and the contents don’t match, an interrupt will be generated.

For example, if setting I/O pin P0.1 to be output and high under fail-safe mode, the sequence to configure fail-safe mode:

1. Configure bit 0 in the Fail-safe Enable Register 1 as 1
2. Configure bit 0 in the Fail-safe Enable Register 2 as 1
3. Set bit 1 (P0.1) in port 0 of Fail-safe Direction Configuration Register 1 for Port-0 to be 1
4. Set bit 1 (P0.1) in port 0 of Fail-safe Direction Configuration Register 2 for Port-0 to be 1
5. Set bit 1 (P0.1) in port 0 of Fail-safe Output Register 1 for Port-0 to be 1
6. Set bit 1 (P0.1) in port 0 of Fail-safe Output Register 2 for Port-0 to be 1
7. Set bit 0 in Fail-safe Redundancy Check Register to be 1
8. Assert RESET/FAIL-SAFE pin