In Burst Mode Transactions, the initial register pointer is specified by the controller device and sent to the peripheral. For subsequent accesses, the register pointer is automatically incremented to the next valid address (second address byte) corresponding to the next port. This automatic address increment continues as long as the CS remains active low and SCLK pulses are received by the peripheral device.

As the burst mode transaction continues sequentially, the register pointer automatically advances the address. If there is no valid register corresponding to the updated register pointer or the register is a read-only type, the data written is ignored. Similarly on the SDO the peripheral will output 0s for a register which is not mapped in the address space of the device.

It is strongly recommended to use burst mode when configuring or accessing the same register for multiple ports together to improve the effective data throughput on the SPI bus.