SCPS311 March 2026
ADVANCE INFORMATION
When an I/O is configured as an input, FETs Q1 and Q2 are off (see Figure 7-2), which creates a high-impedance input.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either supply or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation.