SCPS311 March 2026
ADVANCE INFORMATION
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DGS|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.3.7 Daisy Chain
Multiple TXE8124 devices can be connected in a daisy chain configuration as shown in example implementation Figure 7-3, to expand the number of I/O ports supported. In the daisy chain mode of operation the SDO of the controller is connected to the SDI of the first TXE8124. The SDO of the first TXE8124 is in turn connected to the SDI of the next TXE8124. This connection can be done until the last TXE8124, where the SDO is connected to the SDI of the controller.
Figure 7-3 SPI Daisy Chain DiagramThe controller transmits a header to auto-configure the daisy chain of operation, followed by the register address of the devices in the chain with the register address of the farthest device in the chain (the device furthest from the controller’s SDI and closest to the controller’s SDO) first. The data is transmitted after the address with data for the furthest device first. When receiving the data from the furthest device is received first.
Refer to Figure 7-4 for the frames of daisy chained transaction. The same sequencing is repeated throughout the entire chain until the final device is reached.
Figure 7-4 SPI Daisy Chain Data FrameHeader segment
Bit-15 and 14 in Header segment are the Header ID that is used by the device controller to detect that a header segment is being received. The Header ID bits have the value 01 to indicate this is a Header segment.
Bit-13 is reserved and bits 12 to 0 indicate the number of devices in the chain.
Address segment (Register Address)
Bit 15 indicates SPI mode of operation (1 = Read operation 0 = Write operation). Refer to the first and second byte in Figure 7-5 for the register address.
Status segment
Bit-15 and 14 indicate a status segment and set to 11 to indicate status segment. Bit 13 to 8 indicate the fault status register and bit 7 to 0 are always transmitted as 0.