Table 6-1 Power Supplies

6.2.1 Negative Supply Connections

The negative supply connections are all externally connected together (to GND). The substrate connection is V_SS (pin 10), the analog negative supply is V_{SS_A} (pin 15), the logic negative supply is V_{SS_D} (pin 29), the RF output stage negative supply is V_{SS_TX} (pin 6), and the negative supply for the RF receiver input is V_{SS_RX} (pin 7).

6.2.2 Digital I/O Interface

To allow compatible I/O signal levels, the TRF796x has a separate supply input V_{DD_I/O} (pin 16), with an input voltage range of 1.8 V to 5.5 V. This pin supplies the I/O interface (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, V_{DD_I/O} is connected directly to V_{DD_X} to ensure that the I/O signal levels of the MCU are the same as the internal logic levels of the reader.

6.2.3 Supply Regulator Configuration

The supply regulators can be automatically or manually configured by the control bits. Table 6-2 lists the manual regulator settings for a 5-V system. Table 6-3 lists the manual regulator settings for a 3-V system. Table 6-4 and Table 6-5 list the automatic mode gain settings for 5-V and 3-V systems, respectively.

The automatic mode is the default configuration. In automatic mode, the regulators are automatically set every time the system is activated by asserting the EN input high. The internal regulators are also automatically reconfigured every time the automatic regulator selection bit is set high (on the rising edge).

The application can reset the automatic mode setting from a state in which the automatic setting bit is already high by changing the automatic setting bit from high to low to high. The regulator-configuration algorithm adjusts the regulator outputs 250 mV below the V_IN level, but not higher than 5 V for V_{DD_RF}, 3.5 V for V_{DD_A}, and 3.4 V for V_{DD_X}. This algorithm ensures the highest possible supply voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio). As an example, the application can improve the PSRR if there is a noisy supply voltage from V_{DD_X} by increasing the target voltage difference across the V_{DD_X} regulator as listed for automatic regulator settings in Table 6-4 and Table 6-5.

6.2.4 Power Modes

The chip has seven power states, which are controlled by two input pins (EN and EN2) and three bits in the Chip Status Control register (00h).

The main reader enable input is EN (which has a threshold level of 1 V [minimum]). Any input signal level from 1.8 V to V_IN can be used. When EN is set high, all of the reader regulators are enabled, together with the 13.56-MHz oscillator, and the SYS_CLK output clock for an external MCU.

The auxiliary enable input EN2 has two functions:

• A direct connection from EN2 to V_IN ensures availability of the regulated supply (V_{DD_X}) and an auxiliary clock signal (60 kHz) on the SYS_CLK output (same for the case EN = 0). This mode is intended for systems in which the MCU controlling the reader is also being supplied by the reader supply regulator (V_{DD_X}) and the MCU clock is supplied by the SYS_CLK output of the reader. This lets the MCU supply and clock be available during power down.
• EN2 enables start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this case, the EN input is controlled by the MCU or other system device that is without supply voltage during complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input (which has a 1-V threshold level) starts the reader supply system and 13.56-MHz oscillator (identical to condition EN = 1). This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized. If the EN input is set high by the MCU (or other system device), the reader stays active. If the EN input is not set high within 100 µs after the SYS_CLK output is switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to a complete power-down mode. This option can be used to wake the reader system from complete power down by using a push-button switch or by sending a single pulse.

After the reader EN line is high, the other power modes are selected by control bits. Table 6-6 lists the power mode options and functions.

During reader inactivity, the TRF796x can be placed in power-down mode (EN = 0). The power down can be complete (EN = 0, EN2 = 0) with no function running, or partial (EN = 0, EN2 = 1) with the regulated supply (V_{DD_X}) and 60-kHz auxiliary clock (SYS_CLK) available to the MCU or other system device.

When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1), the supply regulators are activated and the 13.56-MHz oscillator is started. When the supplies are settled and the oscillator frequency is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the selected frequency derived from the crystal oscillator. At this time, the reader is ready to communicate and perform the required tasks. The control system (MCU) can then write appropriate bits to the Chip Status Control register (address 0x00) and select the operation mode.

The standby mode (bit 7 = 1 in register 0x00) is the active mode with the lowest current consumption. The reader can recover from this mode to full operation in 100 µs.

The active mode with RF section disabled (bit 5 = 0 and bit 1 = 0 in register 0x00) is the next active mode with low power consumption. The reader is capable of recovering from this mode to full operation in 25 µs.

The active mode with only the RF receiver section active (bit 1 = 1 in register 0x00) can be used to measure the external RF field (see Section 6.3.1) if reader-to-reader anticollision is implemented.

The active mode with the entire RF section active (bit 5 = 1 in register 0x00) is the normal mode used for transmit and receive operations.

6.2.5 Timing Diagrams

Figure 6-2 shows an oscilloscope trace of chip power up.

Figure 6-3 shows an oscilloscope trace of chip enable to clock start with EN2 low and EN high.

Figure 6-4 shows an oscilloscope trace of chip enable to clock start with EN2 high and EN low.

Figure 6-2 Chip Power Up [V_IN (Blue) to Crystal Start (Red)]

Figure 6-3 Chip Enable to Clock Start, EN2 Low and EN High (Blue) to Start of System Clock (Red)

Figure 6-4 Chip Enable to Clock Start, EN2 High and EN Low (Blue) to Start of System Clock (Red)

6.3.1 Received Signal Strength Indicator (RSSI)

The RSSI measurement block measures the demodulated signal (except in the case of a direct command for RF-amplitude measurement; see Section 6.5). The measuring system latches the peak value, so the RSSI level can be read after the end of the receive packet. The RSSI register values reset with every transmission by the reader. This allows an updated RSSI measurement for each new tag response.

Table 6-7 and Table 6-8 list the correlation between the RF input level and RSSI designation levels on RX_IN1 and RX_IN2.

Table 6-7 compares the RSSI level and the RSSI bit value. The RSSI has seven levels (3 bits each) with 4-dB increments. The input level is the peak-to-peak modulation level of the RF signal as measured on one side envelope (positive or negative).

As an example, from Table 6-8, let B2 = 1, B1 = 1, B0 = 0. This yields an RSSI value of 6. From Table 6-7 a bit value of 6 indicates an RSSI level of 20 mVpp.

6.3.2 Receiver – Digital Section

The received subcarrier is digitized to form a digital representation of the modulated RF envelope. This digitized signal is applied to digital decoders and framing circuits for further processing.

The digital part of the receiver consists of two sections, which partly overlap. The first section consists of the bit decoders for the various protocols, and the second section consists of the framing logic. The bit decoders convert the subcarrier coded signal to a bit stream and also to the data clock. Thus, the subcarrier-coded signal is transformed to serial data, and the data clock is extracted. The decoder logic is designed for maximum error tolerance. This enables the decoders to successfully decode even partly corrupted (due to noise or interference) subcarrier signals.

In the framing section, the serial bit stream data is formatted in bytes. In this process, special signals like the start of frame (SOF), end of frame (EOF), start of communication, and end of communication are automatically removed. The parity bits and CRC bytes are checked and also removed. The end result is clean or raw data, which is sent to the 12-byte FIFO register where it can be read by the external microcontroller system.

The start of the receive operation (successfully received SOF) sets the flags in the IRQ Status register. The end of the receive operation is indicated to the external system (MCU) by sending an interrupt request (pin 13, IRQ). If the receive data packet is longer than 8 bytes, an interrupt is sent to the MCU when the received data occupies 75% of the FIFO capacity to signal that the data should be removed from the FIFO. Use the FIFO Status register (0x1C) to provide the number of bytes that should be clocked out during the actual FIFO read.

If any error in data format, parity, or CRC is detected, the external system is notified of the error by an interrupt-request pulse. The source condition of the interrupt-request pulse is available in the IRQ Status register (address 0x0C) (see Table 6-24).

The ISO Control register (address 0x01) is the primary control for the digital part of the receiver. By writing to this register, the application selects the protocol to be used. With each new write in this register, the default presets are loaded in all related registers, so no further adjustments in other registers are typically needed for proper operation.

Table 6-12 describes the coding of the ISO Control register. The TRF7961 does not include the ISO/IEC 14443 functionality; therefore, the features and commands for this protocol are not functional for the TRF7961.

The framing section also supports bit-collision detection as specified in ISO/IEC 14443 A and ISO/IEC 15693. When a bit collision is detected, an interrupt request is sent and a flag is set in the IRQ Status register. For ISO/IEC 14443 A specifically, the position of the bit collision is written in two registers: partly in the Collision Position register (0x0E) and partly in the Collision Position and Interrupt Mask register (0x0D) (bits B6 and B7). The collision position is presented as a sequential bit number, where the count starts immediately after the start bit. For example, the collision in the first bit of the UID would give the value 00 0001 0000 in the collision position registers. The count starts with 0, and the first 16 bits are the command code and the NVB byte (the NVB byte is the number of valid bits).

The receive section also has two timers. The RX wait time timer is controlled by the value in the RX Wait Time register (address 0x08). This timer defines the time after the end of the transmit operation in which the receive decoders are not active (held in reset state). This prevents incorrect detections resulting from transients following the transmit operation. The value of the RX Wait Time register defines this time in increments of 9.44 µs. This register is preset at every write to ISO Control register (address 0x01) according to the minimum tag-response time defined by each standard.

The RX no response timer is controlled by the RX No Response Wait Time register (address 0x07). This timer measures the time from the start of slot in the anticollision sequence until the start of tag response. If there is no tag response in the defined time, an interrupt request is sent and a flag is set in IRQ Status Control register. This enables the external controller to be relieved of the task of detecting empty slots. The wait time is stored in the register in increments of 37.76 µs. This register is also preset, automatically, for every new protocol selection.

6.3.3 Transmitter

The transmitter section consists of the 13.56-MHz oscillator, digital protocol processing, and RF output stage.

6.3.4 Direct Mode

Direct mode supports two configurations:

Direct mode 0 (bit 6 = 0 in the ISO Control register) enables use of only the front-end functions of the reader, bypassing the protocol implementation in the reader. For transmit functions, the application has direct access to the transmit modulator through the MOD pin (pin 14). On the receive side, the application has direct access to the subcarrier signal (digitized RF envelope signal) on I/O_6 (pin 23).

Direct mode 1 (bit 6 = 1 in the ISO Control register) uses the subcarrier signal decoder of the selected protocol (as defined in the ISO Control register). This means that the receive output is not the subcarrier signal but the decoded serial bit stream and bit clock signals. The serial data is available on I/O_6 (pin 23) and the bit clock is available on I/O_5 (pin 22). The transmit side is identical; the application has direct control over the RF modulation through the MOD input. This mode is provided so that the application can implement a protocol that has the same bit coding as one of the protocols implemented in the reader, but needs a different framing format.

To use direct mode, first select the direct mode to enter by writing B6 in the ISO Control register. This bit determines if the receive output is the direct subcarrier signal (B6 = 0) or the serial data of the selected decoder. If B6 = 1, also define which protocol should be used for bit decoding by writing the appropriate setting in the ISO Control register.

The reader actually enters the direct mode when B6 (direct) is set to 1 in the Chip Status Control register. Direct mode starts immediately. The write command should not be terminated with a stop condition (see communication protocol), because the stop condition terminates the direct mode and clears B6. This is necessary as the direct mode uses one or two I/O pins (I/O_6, I/O_5). Standard parallel communication is not possible in direct mode. Sending a stop condition terminates direct mode.

Figure 6-5 shows mode 0 and mode 1 in direct mode.

• In mode 0, the reader is used as an AFE only, and protocol handling is bypassed.
• In mode 1, framing is not done, but SOF and EOF are present. This allows for a user-selectable framing level based on an existing ISO standard.

In mode 2 (standard mode), data is ISO-standard formatted. SOF, EOF, and error checking are removed, so the microprocessor receives only bytes of raw data through a 12-byte FIFO.

Figure 6-5 User-Configurable Modes

6.3.5 Register Preset

After power up and the EN pin low-to-high transition, the reader is in the default mode. The default configuration is ISO/IEC 15693, single subcarrier, high data rate, 1-out-of-4 operation. The low-level option registers (0x02 to 0x0B) are automatically set to adapt the circuitry optimally to the appropriate protocol parameters.

When entering another protocol (writing to the ISO Control register [0x01]), the low-level option registers (0x02 to 0x0B) are automatically configured to the new protocol parameters.

After selecting the protocol, it is possible to change some low-level register contents if needed. However, changing to another protocol and then back, reloads the default settings, and the application must reload the custom settings.

The Clo1 and Clo0 bits in register 0x09, which define the microcontroller frequency available on the SYS_CLK pin, are the only two bits in the configuration registers that are not cleared during protocol selection.

Table 6-10 Register Address Space

6.4.1 Control Registers – Main Configuration Registers

Table 6-11 describes the Chip Status Control register. This register controls the power mode, RF on or off, and AM or PM. The register default is 0x01 and is reset at EN = L or POR = H.

Table 6-12 describes the ISO Control register. This register controls the ISO selection. The register default is 0x02, which is ISO/IEC 15693 high bit rate, one subcarrier, 1 out of 4. The default is reset at EN = L or POR = H.

6.4.2 Control Registers – Sublevel Configuration Registers

Table 6-14 describes the ISO14443B TX Options register. This register selects the ISO subsets for ISO/IEC 14443 B transmit. The register default is 0x00 and is reset at POR = H or EN = L.

Table 6-15 describes the ISO14443A High-Bit-Rate Options register. The register default is 0x00 and is rest at POR = H or EN = L and at each write to the ISO Control register.

Table 6-16 describes the TX Timer H-Byte register. The register default is 0xC2 and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-17 describes the TX Timer L-Byte register. The register default is 0x00 and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-18 describes the TX Pulse Length Control register. This register controls the length of TX pulse. The register default is 0x00 and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-19 describes the RX No Response Wait Time register. This register defines the time when a no response interrupt is sent. The default is 0x0E and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-20 describes the RX Wait Time register. This register defines the time after TX EOF when the RX input is disregarded. The default is 0x1F and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-21 describes the Modulator and SYS_CLK Control register. This register controls the modulation depth, modulation input, and ASK/OOK pin control. The default is 0x11 and is reset at POR = H or EN = L and at each write to the ISO Control register, except for the Clo1 and Clo0 bits.

Table 6-22 describes the RX Special Setting register. This register sets the gains and filters directly. The default is 0x40 and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-23 describes the Regulator and I/O Control register. This register controls the three voltage regulators. The default is 0x87 and is reset at POR = H or EN = L.

6.4.3 Status Registers

Table 6-24 describes the IRQ Status register. This register displays the cause of IRQ and TX and RX status. The default is 0x00 and is reset at POR = H or EN = L and at each write to the ISO Control register. The register is also automatically set to default at the end of a read phase. This reset also removes the IRQ flag.

Table 6-25 describes the Collision Position and Interrupt Mask register. The default is 0x3E and is reset at POR = H and EN = L. Collision bits are reset automatically after a read operation.

Table 6-26 describes the Collision Position register. This register displays the bit position of collision or error. The default is 0x00 and is reset at POR = H and EN = L. Collision bits are reset automatically after a read operation.

Table 6-27 describes the RSSI Levels and Oscillator Status register. This register reports the signal strength on both reception channels and RF amplitude during RF-off state. The RSSI values are valid from reception start until the start of the next transmission.

6.4.4 FIFO Control Registers

Table 6-28 describes the FIFO Status register. This register reports the low nibbles of complete bytes to be transferred through FIFO, information about a broken byte, and the number of bits to be transferred from it.

Table 6-29 describes the TX Length Byte1 register. This register reports the high 2 nibbles of complete bytes to be transferred through the FIFO. The default is 0x00 and is reset at POR and EN = 0. It is also automatically reset at TX EOF.

Table 6-30 describes the TX Length Byte2 register. This register reports the low nibble of complete bytes to be transferred through the FIFO, information about a broken byte, and the number of bits to be transferred from it. The default is 0x00 and is reset at POR and EN = 0. It is also automatically reset at TX EOF.

6.5.1 Command Codes

Table 6-31 describes the command codes.

6.5.2 Reset FIFO

The Reset FIFO command clears the FIFO contents and FIFO Status register (1Ch) and the Collision Position register (0Eh).

6.5.3 Transmission With CRC

The transmission command must be sent first, followed by transmission length bytes, and then the FIFO data. The reader starts transmitting after the first byte is loaded into the FIFO. The CRC byte is included in the transmitted sequence.

6.5.4 Transmission Without CRC

Same as Section 6.5.3 with CRC excluded.

6.5.5 Delayed Transmission With CRC

The transmission command must be sent first, followed by the transmission length bytes, and then the FIFO data. The reader transmission is triggered by the TX timer.

6.5.6 Delayed Transmission Without CRC

Same as Section 6.5.5 with CRC excluded.

6.5.7 Transmit Next Time Slot

When this command is received, the reader transmits the next slot command. The next slot sign is defined by the protocol selection. This command is used for ISO/IEC 15693 only.

6.5.8 Receiver Gain Adjust

This command should be executed when the MCU determines that no tag response is coming and when the RF and receivers are on. When this command is received, the reader reads the digitized receiver output. If more than two edges are observed in 100 µs, the window comparator voltage is increased. The procedure is repeated until the number of edges (changes of logical state) of the digitized reception signal is less than 2 (in 100 µs). The command can reduce the input sensitivity in 5-dB increments up to 15 dB. This command ensures better operation in a noisy environment.

The gain setting is reset to maximum gain at EN = 0, POR = 1.

6.5.9 Test External RF (RSSI at RX Input With TX Off)

This command can be used in active mode when the RF receiver is on, and the RF output is off (rec-on, bit B1 = 1 in the Chip Status Control register [see Table 6-11]). The level of the RF signal received on the antenna is measured and reported in the RSSI Levels register. The relation between the 3-bit code and the external RF field strength (in A/m) must be determined by calculation or by experiments for each antenna design. The antenna Q and connection to the RF input influence the result. The nominal relationship between the RF peak-to-peak voltage at the receiver inputs and the corresponding RSSI level is as follows.

If the direct command Test RF Internal or Test RF External is used immediately after activation, the command should be preceded by the Enable RX command to activate the RX section. For proper execution of the test RF commands, the RX section must be enabled. This section is enabled automatically when a data exchange between the reader and the tag is done, or by sending the Enable RX direct command.

6.5.10 Test Internal RF (RSSI at RX Input With TX On)

This command measures the level of the RF carrier at the receive inputs. Its operating range is 300 mVp to 2.1 Vp with a step size of 300 mV. The two values are displayed in the RSSI Levels register. The command is intended for diagnostic purposes to set the correct RX_IN levels. The optimum RX_IN input level is approximately 1.6 Vp, or an RSSI level of 5 or 6. The nominal relationship between the input RF peak level and the corresponding RSSI code is as follows.

6.5.11 Block Receiver

The Block Receiver command puts the digital part of receiver (bit decoder and framer) in reset mode. This is useful in an extremely noisy environment, where the noise level could otherwise cause a constant switching of the subcarrier input of the digital part of the receiver. The receiver (if not in reset) would try to catch an SOF signal, and if the noise pattern matched the SOF pattern, an interrupt would be generated, falsely signaling the start of an RX operation. A constant flow of interrupt requests can be a problem for the external system (MCU), so the external system can stop this by putting the receive decoders in reset mode. The reset mode can be terminated in two ways. The external system can send the Enable Receiver command. The reset mode is also automatically terminated at the end of a TX operation. The receiver can stay in reset after end of TX if the RX Wait Time register (address 0x08) is set. In this case, the receiver is enabled at the end of the wait time following the transmit operation.

6.5.12 Enable Receiver

This command clears the reset mode in the digital part of the receiver if the reset mode was entered by the Block Receiver command.

6.6.1 Introduction

The communication interface to the reader can be configured as a parallel 8-pin interface with a data clock or as a serial peripheral interface (SPI). These modes are mutually exclusive; only one mode can be used at a time in the application.

When the SPI is selected, the unused I/O_2, I/O_1, and I/O_0 pins must be hardwired according to Table 6-32. At power up, the TRF7960 IC samples the status of these three pins and then enters one of the possible SPI modes (see Table 6-32).

The reader always acts as the slave while the microcontroller (MCU) acts as the master device. The MCU initiates all communications with the reader and is also used to communicate with the higher levels (application layer). The reader has an IRQ pin to prompt the MCU for attention if the reader detects a response from a proximity integrated circuit card (PICC) or a vicinity integrated circuit card (VICC).

Communication is initialized by a start condition, which is expected to be followed by an Address/Command (Adr/Cmd) word. The Adr/Cmd word is 8 bits long (see Table 6-33).

The MSB (bit 7) determines if the word is to be used as a command or as an address. The ADDRESS and COMMAND columns of Table 6-33 list the function of the separate bits if either address or command is written. Data is expected when the address word is sent. In continuous-address mode (B5  = 1), the first data that follows the address is written to or read from the given address. For each additional data, the address is incremented by 1. Continuous mode can be used to write to a block of control registers in a single stream without changing the address; for example, setup of the predefined standard control registers from the nonvolatile memory of the MCU to the reader. In noncontinuous address mode (simple addressed mode), only one data word is expected after the address.

Address mode is used to write or read the configuration registers or the FIFO. When writing more than 12 bytes to the FIFO, the continuous address mode should be set to 1.

The command mode is used to enter a command resulting in reader action (for example, initialize transmission, enable reader, or turn reader on or off).

The following examples show the expected communication between the MCU and reader.

6.7.1 Receive

At the start of a receive operation (when SOF is successfully detected), B6 is set in the IRQ Status register. An interrupt request is sent to the MCU at the end of the receive operation if the receive data string was shorter than or equal to 8 bytes. The MCU receives the interrupt request, then checks to determine the reason for the interrupt by reading the IRQ Status register (address 0Ch), after which the MCU reads the data from the FIFO.

If the received packet is longer than 8 bytes, the interrupt is sent before the end of the receive operation when the ninth byte is loaded into the FIFO (75% full). The MCU should again read the content of the IRQ Status register to determine the cause of the interrupt request. If the FIFO is 75% full (as marked with flag B5 in the IRQ Status register and by reading the FIFO Status register), the MCU should respond by reading the data from the FIFO to make room for new incoming receive data. When the receive operation is finished, the interrupt is sent and the MCU must check how many words are still present in the FIFO before it finishes reading.

If the reader detects a receive error, the corresponding error flag is set (for example, framing error or CRC error) in the IRQ Status register, which indicates that the MCU reception was completed incorrectly.

6.7.2 Transmit

Before beginning data transmission (see Figure 6-8), the FIFO should be cleared with a reset command (0x0F). Data transmission is initiated with a selected command (see Table 6-31). The MCU then commands the reader to do a continuous write command (3Dh, see Table 6-33) starting from register 1Dh. Data written into register 1Dh is the TX Length Byte1 (upper and middle nibbles), while the next byte in register 1Eh is the TX Length Byte2 (lower nibble and broken byte length). The TX byte length determines when the reader sends the EOF byte. After the TX Length Bytes are written, FIFO data is loaded in register 1Fh with byte storage locations 0 to 11. Data transmission begins automatically after the first byte is written into the FIFO. The loading of TX Length Bytes and the FIFO can be done with a continuous-write command, because the addresses are sequential.

At the start of transmission, the Irq_tx flag (B7) is set in the IRQ Status register. If the transmit data is shorter than or equal to 4 bytes, the interrupt is sent only at the end of the transmit operation. If the number of bytes to be transmitted is greater than or equal to 5, the interrupt is generated. The interrupt is also generated when the number of bytes in the FIFO reaches 3. The MCU should check the IRQ Status register and the FIFO Status register and then load additional data to the FIFO, if needed. At the end of the transmit operation, an interrupt is sent to notify the MCU that the task is complete.

6.8.1 SPI Without SS* (Slave Select) Pin

The serial interface without the slave select pin must use delimiters for the start and stop conditions. Between these delimiters, the address, data, and command words can be transferred. All words must be 8 bits long with MSB transmitted first.

Figure 6-9 Serial – SPI Communication (No SS* Pin)

In this mode, a rising edge on Data IN (I/O_7, pin 24) while SCLK is high resets the serial interface and prepares it to receive data. Data IN can change only when SCLK is low and is taken by the reader on the rising edge of SCLK. Communication is terminated by the stop condition when the falling edge of Data IN occurs during a high SCLK period.

6.8.2 SPI With SS* (Slave Select) Pin

The serial interface is in reset while the SS* signal is high. Serial data-in (MOSI) changes on the falling edge, and is validated in the reader on the rising edge, as shown in Figure 6-10. Communication is terminated when the SS* signal goes high.

All words must be 8 bits long with the MSB transmitted first.

Figure 6-10 Serial – SPI Communication (Write Mode)

Figure 6-11 shows the SPI read operation.

The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data changes on the falling edge, and is validated in the reader on the rising edge (see Figure 6-11). During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is validated at the eighth rising edge of SCLK, after half a clock cycle, valid data can be read on the MISO pin at the falling edge of SCLK. It takes eight clock edges to read out the full byte (MSB first).

The MOSI (serial data out) should not have any transitions (all high or all low) during the read cycle. Also, the SS* signal should be low during the whole write and read operation.

Figure 6-12 shows the continuous read operation.

Figure 6-12 SPI Communication (Continuous Read Mode)

Figure 6-13 SPI Communication (IRQ Status Register Read)