7.3.1 Battery Charger

The TPS65012 supports a precision Li-Ion or Li-Polymer charging system suitable for single cells with either coke or graphite anodes. Charging the battery is possible even without the application processor being powered up. The TPS65012 starts charging when an input voltage on either AC or USB input is present, which is greater than the charger UVLO threshold. See Figure 26 for a typical charge profile.

Figure 26. Typical Charging Profile

7.3.1.2 Temperature Qualification

The TPS65012 continuously monitors battery temperature by measuring the voltage between the TS and AGND pins. An internal current source provides the bias for most common 10K negative-temperature coefficient thermistors (NTC) (see Figure 27). The IC compares the voltage on the TS pin against the internal V_(LTF) and V_(HTF) thresholds to determine if charging is allowed. Once a temperature outside the V_(LTF) and V_(HTF) thresholds is detected, the IC immediately suspends the charge. The IC suspends charge by turning off the power FET and holding the timer value (i.e., timers are not reset). Charge is resumed when the temperature returns to the normal range.

The allowed temperature range for 103-A T-type thermistor is 0°C to 45°C. However, the user may modify these thresholds by adding two external resistors. See Figure 28.

Figure 27. TS Pin Configuration

Figure 28. TS Pin Threshold

7.3.2 Step-Down Converters, VMAIN and VCORE

The TPS65012 incorporates two synchronous step-down converters operating typically at 1.25 MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter power-save mode and operate with pulse frequency modulation (PFM). The main converter is capable of delivering 1-A output current, and the core converter is capable of delivering 400 mA.

The converter output voltages are programmed via the VDCDC1 and VDCDC2 registers in the serial interface. The main converter defaults to 3-V or 3.3-V output voltage depending on the DEFMAIN configuration pin, if DEFMAIN is tied to ground, the default is 3 V; if it is tied to V_CC the default is 3.3 V. The core converter defaults to either 1.5 V or 1.6 V depending on whether the DEFCORE configuration pin is tied to GND or to V_CC, respectively. Both the main and core output voltages can subsequently be reprogrammed after start-up via the serial interface. In addition, the LOW_PWR pin can be used either to lower the core voltage to a value defined in the VDCDC2 register when the application processor is in deep sleep mode or to disable the core converter. An active signal at LOW_PWR is ignored if the ENABLE_LP bit is not set in the VDCDC1 register.

The step-down converter outputs (when enabled) are monitored by power-good comparators, the outputs of which are available via the serial interface. The outputs of the DC-DC converters can be optionally discharged when the DC-DC converters are disabled.

During PWM operation, the converters use a unique fast-response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the dead time preventing current shoot through, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel switch.

The error amplifier, together with the input voltage, determines the rise time of the saw-tooth generator, and therefore, any change in input voltage or output voltage directly controls the duty cycle of the converter giving a good line and load transient regulation.

The two DC-DC converters operate synchronized to each other, with the MAIN converter as the master. A 270° phase shift between the MAIN switch turn on and the CORE switch turn on decreases the input RMS current, and smaller input capacitors can be used. This is optimized for a typical application where the MAIN converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V and the CORE from 3.7 V to 1.5 V.

7.3.2.1 Power-Save Mode Operation

As the load current decreases, the converter enters the power-save mode operation. During power save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency.

In order to optimize the converter efficiency at light load, the average current is monitored; if in PWM mode, the inductor current remains below a certain threshold, then power-save mode is entered. The typical threshold can be calculated as:

Equation 1.

During the power-save mode, the output voltage is monitored with the comparator by the thresholds comp low and comp high. As the output voltage falls below the comp-low threshold, set to typically 0.8% above the nominal V_out, the P-channel switch turns on. The converter then runs at 50% of the nominal switching frequency. If the load is below the delivered current, then the output voltage rises until the comp-high threshold is reached, typically 1.6% above the nominal V_out. At this point, all switching activity ceases, hence reducing the quiescent current to a minimum until the output voltage has dropped below comp low again. If the load current is greater than the delivered current, then the output voltage falls until it crosses the nominal output voltage threshold (comp-low 2 threshold), whereupon power-save mode is exited, and the converter returns to PWM mode.

These control methods reduce the quiescent current typically to 12-µA per converter and the switching frequency to a minimum achieving the highest converter efficiency. Setting the comparator thresholds to typically 0.8% and 1.6% above the nominal output voltage at light load current results in a dynamic voltage positioning achieving lower absolute voltage drops during heavy load transient changes. This allows the converters to operate with a small output capacitor of just 10 µF for the core and 22 µF for the main output and still have a low absolute voltage drop during heavy load transient changes. See Figure 29 for detailed operation of the power-save mode. The power-save mode can be disabled through the I²C interface to force the converters to stay in fixed frequency PWM mode.

Figure 29. Power-Save Mode Thresholds and Dynamic Voltage Positioning

7.3.2.5 100% Duty Cycle Low-Dropout Operation

The TPS65012 converters offer a low input to output voltage difference while maintaining operation with the use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage and is calculated as:

Equation 2.

where

• I_O(max) = maximum output current plus inductor ripple current
• r_DS(on)max= maximum P-channel switch r_DS(on).
• R_L = DC resistance of the inductor
• V_O(max)= nominal output voltage plus maximum output voltage tolerance

7.3.3 Low-Dropout Voltage Regulators

The low-dropout voltage regulators are designed to operate with low value ceramic input and output capacitors. They operate with input voltages down to 1.8 V. The LDOs offer a maximum dropout voltage of 300 mV at rated output current. Each LDO has a current limit feature. Both LDOs are enabled per default; both LDOs can be disabled or programmed via the serial interface using the VREGS1 register. The LDO outputs (when enabled) are monitored by power-good comparators, the outputs of which are available via the serial interface. The LDOs also have reverse conduction prevention when disabled. This allows the possibility to connect external regulators in parallel in systems with a backup battery.

7.3.4 Undervoltage Lockout

The undervoltage lockout circuit for the four regulators on TPS65012 prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. Basically, it prevents the converter from turning on the power switch or rectifier FET under undefined conditions. The undervoltage threshold voltage is set by default to 3.25 V. After power up, the threshold voltage can be reprogrammed through the serial interface. The undervoltage lockout comparator compares the voltage on the VCC pin with the UVLO threshold. When the VCC voltage drops below this threshold, the TPS65012 sets the PWRFAIL pin low and after a time t_(UVLO) disables the voltage regulators in the sequence defined by PS_SEQ. The same procedure is followed when the TPS65012 detects that its junction temperature has exceeded the overtemperature threshold, typically 160°C, with a delay t_(overtemp). The TPS65012 automatically restarts when the UVLO (or overtemperature) condition is no longer present.

The battery charger circuit has a separate UVLO circuit with a threshold of typically 2.5 V, which is compared with the voltage on AC and USB supply pins.

7.3.5 Power-Up Sequencing

The TPS65012 power-up sequencing allows the maximum flexibility without generating excessive logistical or system complexity. The relevant control pins are described in the following table:

Figure 30 shows the state diagram for the TPS65012 power sequencing. The charger function is not shown in the state diagram because this function is independent of these states.

Figure 30. TPS65012 Power-On State Diagram

7.3.6 System Reset and Control Signals

The RESPWRON signal is used as a global reset for the application. It is an open-drain output. The RESPWRON signal is generated according to the power-good comparator linked to VLDO1 and remains low for t_n(RESPWRON) seconds after VLDO1 has stabilized. When RESPWRON is low, PWRFAIL, MPU_RESET and INT are also held low.

If the output voltage of LDO1 is less than 90% of its nominal value, as RESPWRON is generated, and if the output voltage of LDO1 is programmed to a higher value, which causes the output voltage to fall out of the 90% window, then a RESPWRON signal is generated.

The PWRFAIL signal indicates when VCC < UVLO or when the TPS65012 junction temperature has exceeded a reliable value or if BATT_COVER is taken low. This open-drain output can be connected at a fast interrupt pin for immediate attention by the application processor. All supplies are disabled t(_uvlo), t_(overtemp) or t_{(batt_cover)} seconds after PWRFAIL has gone low, giving time for the application processor to shut down cleanly.

The BATT_COVER function detects whether the battery cover is in place or not. If the battery cover is removed, the TPS65012 generates a warning to the processor that the battery is likely to be removed and that it may be prudent to shut down the system. If not required, this feature may be disabled by connecting the BATT_COVER pin to the VCC pin. BATT_COVER is de-bounced internally. Typical de-bounce time is 56 ms. BATT_COVER has an internal 2-MΩ pulldown resistor.

The HOT_RESET input is used to generate an MPU_RESET signal for the application processor. The HOT_RESET pin could be connected to a user-activated button in the application. It can also be used to exit low-power mode. In this case, the TPS65012 waits until the VCORE voltage has stabilized before generating the MPU_RESET pulse. The MPU_RESET pulse is active low for t_{(mpu_nreset)} seconds. HOT_RESET has an internal 1-MΩ pullup resistor to V_CC.

The PB_ONOFF input can be used to exit LOW-POWER MODE. It is typically driven by a user-activated push-button in the application. Both HOT_RESET and PB_ONOFF are de-bounced internally by the TPS65012. Typical de-bounce time is 56 ms. PB_ONOFF has an internal 1-MΩ pulldown resistor.

PB_ONOFF, BATT_COVER and UVLO events also cause a normal, maskable interrupt to be generated and are noted in the REGSTATUS register.

7.3.7 Vibrator Driver

The VIB open-drain output is provided to drive a vibrator motor, controlled via the serial interface register VDCDC2. It has a maximum dropout of 0.5 V at 100-mA load. Typically, an external resistor is required to limit the motor current and a freewheel diode to limit the VIB overshoot voltage at turnoff.

7.4.1 TPS65012 Power States Description

7.4.1.4 State 4: Shutdown

WAIT mode can be entered from any of the above states when fault conditions exist:

1. From State 1 when a discharged battery is applied.
2. From States 2 and 3 if an OVERTEMP condition exists.
3. If VCC drops below the UVLO threshold.
4. If BATT_COVER goes low indicating that the battery is about to be removed.

WAIT mode can also be initiated by the processor. This is done by setting the ENABLE SUPPLY bit (VDCDC1 register) low, the ENABLE LP bit (also VDCDC1 register) high, and then raising the low-power pin. When this occurs, the VMAIN and VCORE converters are powered down according to PS_SEQ. The LDOs can remain enabled in reduced quiescent current operation or be programmed to turn off in WAIT mode. If all supplies are disabled and both VMAIN and VCORE are discharged close to ground, then the voltage reference circuitry is disabled and the serial interface registers reset to their default values. WAIT mode is left by activating either the PB_ONOFF or HOT_RESET pins. For this to be successful, the voltage at VCC must exceed the UVLO threshold, and the BATT_COVER pin must be high.

Table 4 indicates the typical quiescent current consumption in each power state.

Table 4. TPS65012 Typical Current Consumption

STATE	TOTAL QUIESCENT CURRENT	QUIESCENT CURRENT BREAKDOWN
1	0
2	30 µA-70 µA	VMAIN (12 µA) + VCORE (12 µA) + LDOs (20 µA each, max 2) + UVLO + reference + PowerGood
3	30 µA-55 µA	VMAIN (12 µA) + VCORE (12 µA) + LDOs (10 µA each, max 2) + UVLO + reference + PowerGood
4	13 µA	UVLO + reference circuitry

Figure 31. State 1 to State 2 Transition (PS_SEQ=0, V_CC > V_UVLO + HYST)

Valid for LDO1 supplied from VMAIN as described in Application Information.

If 2.4 ms after application, V_CC is still below the default UVLO threshold (3.425 V for V_CC rising), then start-up is as shown in Figure 32.

Figure 32. State 1 to State 4 to State 2 Transition (Power-Up Behavior When V_CC Ramp is Longer Than 2.4 ms)

Valid for LDO1 supplied from VMAIN as described in Application Information.

Figure 33. State 2 to State 4 Transition

Valid for LDO1 supplied from VMAIN as described in Application Information.

Figure 34. State 2 to State 3 Transition. VCORE Lowered, LDO2 Disabled. Subsequent State 3 to State 2 Transition When LOW-POWER Is De-Asserted.

NOTE

If both LDOs are turned off in low-power mode, the low-power mode can only be exited by activating HOT_RESET or PB_ONOFF.

Figure 35. State 3 to State 2 Transition. PB_ONFF Activated (See Interrupt Management for INT Behavior)

Figure 36. State 3 to State 2 Transition (HOT_RESET Activated, See Interrupt Management for INT Behavior)

Figure 37. State 2 to State 4 Transition

7.5.1 LED2 Output

The LED2 output can be programmed in the same way as the PG output to blink or to be permanently on or off. The LED2_ON and LED2_PER registers are used to control the blink rate. For both PG and LED2, the minimum blink-on time is 10 ms. This can be increased in 127 10-ms steps to 1280 ms. For both PG and LED2, the minimum blink period is 100 ms. This can be increased in 127 100-ms steps to 12800 ms.

7.5.2 Interrupt Management

The open-drain INT pin is used to combine and report all possible conditions via a single pin. Battery and chip temperature faults, precharge timeout, charge timeout, taper timeout, and termination current are each capable of setting INT low, i.e., active. INT can also be activated if any of the regulators are below the regulation threshold. Interrupts can also be generated by any of the GPIO pins programmed to be inputs. These inputs can be programmed to generate an interrupt either at the rising or falling edge of the input signal. It is possible to mask an interrupt from any of these conditions individually by setting the appropriate bits in the MASK1, MASK2, or MASK3 registers. By default, all interrupts are masked. Interrupts are stored in the CHGSTATUS, REGSTATUS, and DEFGPIO registers in the serial interface. CHGSTATUS and REGSTATUS interrupts are acknowledged by reading these registers. If a 1 is present in any location, then the TPS65012 automatically sets the corresponding bit in the ACKINT1 or ACKINT2 registers and releases the INT pin. The ACKINT register contents are self-clearing when the condition, which caused the interrupt, is removed. The applications processor should not normally need to access the ACKINT1 or ACKINT2 registers.

Interrupt events are always captured; thus when an interrupt source is unmasked, INT may immediately go active due to a previous interrupt condition. This can be prevented by first reading the relevant STATUS register before unmasking the interrupt source.

If an interrupt condition occurs, then the INT pin is set low. The CHGSTATUS, REGSTATUS, and DEFGPIO registers should be read. Bit positions containing a 1 (or possibly a 0 in DEFGPIO) are noted by the CPU and the corresponding situation resolved. The reading of the CHGSTATUS and REGSTATUS registers automatically acknowledges any interrupt condition in those registers and blocks the path to the INT pin from the relevant bit(s). No interrupt should be missed during the read process because this process starts by latching the contents of the register before shifting them out at SDAT. Once the contents have been latched (takes a couple of nanoseconds), the register is free to capture new interrupt conditions. Hence, the probability of missing anything is, for practical purposes, zero.

The following describes how registers 0x01 (CHGSTATUS) and 0x02 (REGSTATUS) are handled:

• CHGSTATUS(5,0) are positive edge set. Read of set CHGSTATUS(5,0) bits sets ACKINT1(5,0) bits.
• CHGSTATUS(7-6,4-1) are level set. Read of set CHGSTATUS(7-6,4-1) bits sets ACKINT1(7-6,4-1) bits.
• CHGSTATUS(5,0) clear when input signal low, and ACKINT1(5,0) bits are already set.
• CHGSTATUS(7-6,4-1) clear when input signal is low.
• ACKINT1(7-0) clear when CHGSTATUS(7-0) is clear.
• REGSTATUS(7-5) are positive edge set. Read of set REGSTATUS(7-5) bits sets ACKINT2(7-5) bits.
• REGSTATUS(3-0) are level set. Read of set REGSTATUS(3-0) bits sets ACKINT2(3-0) bits.
• REGSTATUS(7-5) clear when input signal low, and ACKINT1(7-5) bit are already set.
• REGSTATUS(3-0) clear when input signal is low.
• ACKINT2(7-0) clear when REGSTATUS(7-0) is clear.

The following describes the function of the 0x05 (ACKINT1) and 0x06 (ACKINT2) registers. These are not usually written to by the CPU since the TPS65012 internally sets/clears these registers:

• ACKINT1(7:0) - Bit is set when the corresponding CHGSTATUS set bit is read via I²C.
• ACKINT1(7:0) - Bit is cleared when the corresponding CHGSTATUS set bit clears.
• ACKINT2(7:0) - Bit is set when the corresponding REGSTATUS set bit is read via I²C.
• ACKINT2(7:0) - Bit is cleared when the corresponding REGSTATUS set bit clears.
• ACKINT1(7:0) - a bit set masks the corresponding CHGSTATUS bit from INT.
• ACKINT2(7:0) - a bit set masks the corresponding REGSTATUS bit from INT.

The following describes the function of the 0x03 (MASK1), 0x04 (MASK2) and 0x0F (MASK3) registers:

• MASK1(7:0) - a bit set in this register masks CHGSTATUS from INT.
• MASK2(7:0) - a bit set in this register masks REGSTATUS from INT.
• MASK3(7:4) - a bit set in this register detects a rising edge on GPIO.
• MASK3(7:4) - a bit cleared in this register detects a falling edge on GPIO.
• MASK3(3:0) - a bit set in this register clears GPIO detect signal from INT.

GPIO interrupts are located by reading the 0x10 (DEFGPIO) register. The application CPU stores, or can read from DEFGPIO<7:4>, which GPIO is set to input or output. This information together with the information on which edge the interrupt was generated (the CPU either knows this or can read it from MASK3<7:4>) determines whether the CPU is looking for a 0 or a 1 in DEFGPIO<3:0>. A GPIO interrupt is blocked from the INT pin by setting the relevant MASK3<3:0> bit; this must be done by the CPU; there is no auto-acknowledge for the GPIO interrupts.

7.5.3 Serial Interface

The serial interface is compatible with the standard and fast mode I²C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as V_CC remains above 2 V. The TPS65012 has a 7-bit address with the LSB set by the IFLSB pin; this allows the connection of two devices with the same address to the same bus. The 6 MSBs are 100100. Attempting to read data from register addresses not listed in this section results in FFh being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65012 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65012 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65012 device must leave the data line high to enable the master to generate the stop condition.

Figure 38. Bit Transfer on the Serial Interface

Figure 39. START and STOP Conditions

Figure 40. Serial Interface WRITE to TPS65012 Device

Figure 41. Serial Interface READ From TPS65012: Protocol A

Figure 42. Serial Interface READ From TPS65012: Protocol B

7.6.1 CHGSTATUS Register (Address: 01h—Reset: 00h)

The CHGSTATUS register contents indicate the status of charge.

B1-4 may be reset via the serial interface in order to force a reset of the charger. Any attempt to write to B0 and B5-7 is ignored. A 1 in B<7:0> sets the INT pin active unless the corresponding bit in the MASK register is set.

7.6.2 REGSTATUS Register (Address: 02h—Reset: 00h)

Bit 4 - not implemented

A rising edge in the REGSTATUS register contents causes INT to be driven low if it is not masked in the MASK2.

7.6.3 MASK1 Register (Address: 03h—Reset: FFh)

The MASK1 register is used to mask all or any of the conditions in the corresponding CHGSTATUS<7:0> positions being indicated at the INT pin. Default is to mask all.

7.6.4 MASK2 Register (Address: 04h—Reset: FFh)

The MASK2 register is used to mask all or any of the conditions in the corresponding REGSTATUS<7:0> positions being indicated at the INT pin. Default is to mask all.

7.6.5 ACKINT1 Register (Address: 05h—Reset: 00h)

The ACKINT1 register is internally used to acknowledge any of the interrupts in the corresponding CHGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT pin, and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes high, else it remains low. A 1 at any position in ACKINT1 is automatically cleared when the corresponding interrupt condition in CHGSTATUS is removed. The application processor should not normally need to access the ACKINT1 register.

7.6.6 ACKINT2 Register (Address: 06h—Reset: 00h)

The ACKINT2 register is internally used to acknowledge any of the interrupts in the corresponding REGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes high, else it remains low. A 1 at any position in ACKINT2 is automatically cleared when the corresponding interrupt condition in REGSTATUS is removed. The application processor should not normally need to access the ACKINT2 register.

7.6.7 CHGCONFIG Register Address: 07h—Reset: 1Bh

The CHGCONFIG register is used to configure the charger.

This bit must be set, and then reset via the serial interface.

7.6.8 LED1_ON Register (Address: 08h—Reset: 00h)

The LED1_ON and LED1_PER registers can be used to take control of the PG open-drain output normally controlled by the charger.

Bit 7 - PG1: Control of the PG pin is determined by PG1 and PG2 according to the table under LED1_PER register

Bit 6 - BIT 0 LED1_ON<6:0> are used to program the on-time of the open-drain output transistor at the PG pin. The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on-time.

7.6.9 LED1_PER Register (Address: 09h—Reset: 00h)

Bit 7 - PG2: Control of the PG pin is determined by PG1 and PG2 according to the following table.

Bit 6-Bit 0 LED1_PER<6:0> are used to program the time period of the open-drain output transistor at the PG pin. The minimum period is typically 100 ms and one LSB corresponds to a 100-ms step change in the period.

7.6.10 LED2_ON Register (Address: 0Ah—Reset: 00h)

The LED2_ON and LED2_PER registers are used to control the LED2 open-drain output.

Bit 7 LED22: Control is determined by LED21 and LED22 according to the table under LED2_PER register.

Bit 6-Bit 0 LED2_ON<6:0> are used to program the on-time of the open-drain output transistor at the LED2 pin. The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on-time.

7.6.11 LED2_PER (Register Address: 0Bh—Reset: 00h)

Bit 7 LED22: Control is determined by LED21 and LED22 according to the table.

Bit 6-Bit 0 - LED2_PER<6:0> are used to program the on-time of the open-drain output transistor at the LED2 pin. The minimum on-time is typically 100 ms and one LSB corresponds to a 100-ms step change in the on-time.

7.6.12 VDCDC1 Register (Address: 0Ch—Reset: 72h/73h)

The VDCDC1 register is used to program the VMAIN switching converter.

Bit 6-Bit 5 - UVLO<1:0>: The undervoltage threshold voltage is set by UVLO1 and UVLO0 according to Table 20.

Bit 1-Bit 0 - MAIN<1:0>: The VMAIN converter output voltages are set according to Table 21, with the reset in bold set by the DEFMAIN pin. The default voltage can subsequently be overwritten via the serial interface after start-up.

7.6.13 VDCDC2 Register (Address: 0Dh—Reset: 68h/78h)

The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8 steps between 0.85 V and 1.6 V. The reset is governed by the DEFCORE pin; DEFCORE=0 sets an output voltage of 1.5 V. DEFCORE=1 sets an output voltage of 1.6 V.

Bit 6-Bit 4 - CORE<2:0>: The following table shows all possible values of VCORE. The reset can subsequently be overwritten via the serial interface after start-up.

Bit 3-Bit 2 - CORELP<1:0>: CORELP1 and CORELP0 can be used to set the VCORE voltage in low-power mode. In low-power mode, CORE2 is effectively '0'; CORE1 and CORE0 take on the values programmed at CORELP1 and CORELP0, default '10' giving VCORE = 1.1 V as default in low-power mode. When low-power mode is exited, VCORE reverts to the value set by CORE2, CORE1, and CORE0.

7.6.14 VREGS1Register (Address: 0Eh—Reset: 88h)

The VREGS1 register is used to program and enable LDO1 and LDO2 and to set their behavior when low-power mode is active. The LDO output voltages can be set either on the fly, while the relevant LDO is disabled, or simultaneously when the relevant enable bit is set. Note that both LDOs are per default ON.

Bit 7-Bit 6 - The function of the LDO2 enable and LDO2 OFF/nSLP bits is shown in Table 25. See the power-on sequencing section for details of low-power mode.

Bit 5-Bit 4 - LDO2<1:0>: LDO2 has a default output voltage of 1.8 V. If so desired, this can be changed at the same time as it is enabled via the serial interface.

Bit 3-Bit 2 - The function of the LDO1 enable and LDO1 OFF/nSLP bits is shown in the following table. See the power-on sequencing section for details of low-power mode. Note that programming LDO1 to a higher voltage may force a system power-on reset if the increase is in the 10% or greater range.

Bit 1-Bit 0 - LDO1<1:0>: The LDO1 output voltage is per default set externally. If so desired, this can be changed via the serial interface. The adjustable range is 0.9 V to VINLDO1.

7.6.15 MASK3 Register (Address: 0Fh—Reset: 00h)

The MASK3 register must be considered when any of the GPIO pins are programmed as inputs.

Bit 3-Bit 0 - Mask GPIO<4:1>: can be used to mask the corresponding interrupt. Default is unmasked (MASK3<0:3> =0).

7.6.16 DEFGPIO Register Address: (10h—Reset: 00h)

The DEFGPIO register is used to define the GPIO pins to be either input or output.