8.2.2.1 Custom Design with WEBENCH® Tools

Click here to create a custom design using the TPS54561-Q1 device with the WEBENCH® Power Designer.

1. Start by entering your V_IN, V_OUT, and I_OUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability.
4. In most cases, you will also be able to:
   • Run electrical simulations to see important waveforms and circuit performance
   • Run thermal simulations to understand the thermal performance of your board
   • Export your customized schematic and layout into popular CAD formats
   • Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Selecting the Switching Frequency

The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest switching frequency possible because this produces the smallest solution size. High switching frequency allows for lower-value inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. Several factors including the minimum controllable on-time of the internal power switch, the input voltage, the output voltage, and the frequency-foldback protection limit the switching frequency that the designer can select.

Use Equation 12 and Equation 13 to calculate the upper limit of the switching frequency for the regulator. Choose the lower-value result from the two equations. Switching frequencies higher than these values result in pulse-skipping or the lack of overcurrent protection during a short circuit.

The typical minimum controllable on-time, t_(ON), is 100 ns for the TPS54561-Q1 device. For this example, the output voltage is 5 V and the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 955 kHz to avoid pulse skipping from Equation 28. To ensure overcurrent runaway is not a concern during short circuits, use Equation 29 to determine the maximum switching frequency for frequency foldback protection. With a maximum input voltage of 60 V, assuming a diode voltage of 0.7 V, inductor resistance of 11 mΩ, switch resistance of 87 mΩ, a current limit value of 6 A, and short-circuit output voltage of 0.1 V, the maximum switching frequency is 1151 kHz.

For this design, choose a lower switching frequency of 400 kHz to operate comfortably below the calculated maximums. To determine the timing resistance for a given switching frequency, use Equation 10, or the curve in Figure 6, or the curve in Figure 7. Resistor R3 sets the switching frequency shown in Figure 46. For 400-kHz operation, the closest standard value resistor is 243 kΩ.

Equation 28.

Equation 29.

Equation 30.

8.2.2.3 Output Inductor Selection (L_(O))

To calculate the minimum value of the output inductor, use Equation 31.

k_(IND) is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The output capacitor filters the inductor ripple current. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor, because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer. However, the designer may use the following guidelines.

For designs using low-ESR output capacitors such as ceramics, a value as high as k_(IND) = 0.3 may be desirable. When using higher-ESR output capacitors, k_(IND) = 0.2 yields better results. Because the inductor ripple current is part of the current-mode PWM control system, the inductor ripple current should always be greater than 150 mA for stable PWM operation. In a wide-input voltage regulator, choosing a relatively large inductor ripple current is best to provide sufficient ripple current with the input voltage at the minimum.

For this design example, k_(IND) = 0.3 and the calculated inductor value is 7.6 µH. The nearest standard value is 7.2 µH. It is important not to exceed both the rms current and saturation-current ratings of the inductor. Equation 33 and Equation 34 calculate the rms and peak inductor current. For this design, the rms inductor current is 5.021 A and the peak inductor current is 5.817 A. The chosen inductor has an rms current rating of 6 A and a saturation current rating of 7.9 A.

As the equation set demonstrates, lowering ripple currents reduces the output voltage ripple of the regulator but requires a larger value of inductance. Selecting higher ripple currents increases the output-voltage ripple of the regulator but allows for a lower inductance value.

The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults, or transient load conditions, the inductor current can increase above the peak inductor current level calculated previously. In transient conditions, the inductor current can increase up to the switch-current limit of the device. For this reason, the most-conservative design approach is to choose an inductor with a saturation current rating equal to or greater than the switch-current limit of the TPS54561-Q1 device, which is nominally 7.5 A.

Equation 31.

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Equation 32.

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Equation 33.

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Equation 34.

8.2.2.4 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and the regulator response to a large change in load current. It is necessary to select the output capacitance based on the most-stringent of these three criteria.

The desired response to a large change in the load current is the first criterion. The output capacitor must supply the increased load current until the regulator responds to the load step. The regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. The output capacitance must be large enough to supply the difference in current for two clock cycles to maintain the output voltage within the specified range. Equation 35 shows the minimum output capacitance necessary, where ΔI_O is the change in output current, f_(sw) is the regulator switching frequency, and ΔV_O is the allowable change in the output voltage. For this example, the transient load response specification is 4% change in V_O for a load step from 1.25 A to 3.75 A. Therefore, ΔI_O is 3.75 A – 1.25 A = 2.5 A, and ΔV_O = 4% × 5 V = 0.2 V. Using these numbers gives a minimum capacitance of 62.5 µF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore. Aluminum electrolytic and tantalum capacitors have higher ESR, and load-step calculations must include the ESR term.

Sizing of the output capacitor must be such as to absorb energy stored in the inductor when transitioning from a high to low load current. The catch diode of the regulator cannot sink current, so energy stored in the inductor can produce an output voltage overshoot when the load current rapidly decreases. Figure 51 shows a typical load-step response. The excess energy absorbed in the output capacitor increases the voltage on the capacitor. Sizing of the capacitor must be such as to maintain the desired output voltage during these transient periods. Equation 36 calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where L_(O) is the value of the inductor, I_OH is the output current under heavy load, I_OL is the output under light load, V_P is the peak output voltage, and V_(int) is the initial voltage. For this example, the worst-case load step is from 3.75 A to 1.25 A. The output voltage increases during this load transition, and the stated maximum in our specification is 4% of the output voltage. This makes V_(P) = 1.04 × 5 V = 5.2 V. V_(int) is the initial capacitor voltage which is the nominal output voltage of 5 V. Using these numbers in Equation 36 yields a minimum capacitance of 44.1 µF.

Equation 37 calculates the minimum output capacitance needed to meet the output-voltage ripple specification, where f_(SW) is the switching frequency, V_O(RIPPLE) is the maximum allowable output voltage ripple, and I_O(RIPPLE) is the inductor ripple current. Equation 37 yields 19.9 µF.

Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 38 indicates the ESR should be less than 15.7 mΩ.

The most stringent criterion for the output capacitor is 62.5 µF, required to maintain the output voltage within regulation tolerance during a load transient.

Capacitance de-ratings for aging, temperature, and dc bias increase this minimum value. For this example, the selection is three 47-µF, 10-V ceramic capacitors with 5 mΩ of ESR. The derated capacitance is 87.4 µF, well above the minimum required capacitance of 62.5 µF.

Capacitors generally have a maximum ripple-current rating. Filtering a ripple current equal to or below that maximum ripple current does not degrade capacitor reliability. Some capacitor data sheets specify the root-mean-square (rms) value of the maximum ripple current. Use Equation 39 to calculate the rms ripple current that the output capacitor must support. For this example, Equation 39 yields 459 mA.

Equation 35.

Equation 36.

Equation 37.

Equation 38.

Equation 39.

8.2.2.5 Catch Diode

The TPS54561-Q1 device requires an external catch diode between the SW pin and GND. The selected diode must have a reverse voltage rating equal to or greater than maximum input voltage. The peak current rating of the diode must be greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode because of the low forward voltage of these diodes. The lower the forward voltage of the diode, the higher the efficiency of the regulator.

Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of 60-V reverse voltage is preferable, to allow input voltage transients up to the rated voltage of the TPS54561-Q1 device.

For the example design, select the Schottky diode for its lower forward voltage and good thermal characteristics compared to smaller devices. The typical forward voltage of the diode is 0.52 V at 5 A.

One must select the diode with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. Multiplying the output current during the off-time with the forward voltage of the diode can calculate the instantaneous conduction losses of the diode. At higher switching frequencies, take the ac losses of the diode into account. The ac losses of the diode are because of the charging and discharging of the junction capacitance, and also of reverse-recovery charge. Use Equation 40 to calculate the total power dissipation, including conduction losses and ac losses of the diode.

The selected diode has a junction capacitance of 180 pF. Using Equation 40 with the nominal input voltage of 12 V, the total loss in the diode is 1.65 W.

If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode which has a low leakage current and slightly higher forward voltage drop.

Equation 40.

8.2.2.6 Input Capacitor

The TPS54561-Q1 device requires a high-quality ceramic type X5R or X7R input decoupling capacitor with at least 3 µF of effective capacitance. Some applications benefit from additional bulk capacitance. The effective capacitance includes any loss of capacitance because of dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater than the maximum input current ripple of the TPS54561-Q1 device. Use Equation 41 to calculate the input ripple current.

The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor. Selecting a dielectric material that is more stable over temperature can minimize the capacitance variations because of temperature. The usual selection for capacitors in a switching regulator is X5R or X7R ceramic dielectric, because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The input capacitor selection must also consider the dc bias. The effective value of a capacitor decreases as the dc bias across a capacitor increases.

This example design requires a ceramic capacitor with at least a 60-V voltage rating to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or 100 V. For this example, use four 2.2-µF, 100-V capacitors in parallel.

The input capacitance value determines the input ripple voltage of the regulator. Use Equation 42 to calculate the input voltage ripple. Using the design example values, I_O = 5 A, C_(I) = 8.8 µF, f_(sw) = 400 kHz, yields an input voltage ripple of 355 mV and an rms input ripple current of 2.26 A.

Equation 41.

Equation 42.

8.2.2.7 Soft-Start Capacitor

The soft-start capacitor determines the minimum amount of time for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. Adjustable soft-start is also useful if the output capacitance is large and would require large amounts of current to charge the capacitor quickly to the output-voltage level. The large currents necessary to charge the output capacitor may make the TPS54561-Q1 device reach the current limit, or the excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output-voltage slew rate solves both of these problems.

The soft-start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Use Equation 43 to find the minimum soft-start time, t_(SS), necessary to charge the output capacitor, C_(O), from 10% to 90% of the output voltage, V_O, with an typical soft-start current of I_(SS). In the example, to charge the effective output capacitance of 87.4 µF up to 5 V with an average current of 1 A requires a 0.3-ms soft-start time.

After selecting the soft-start time, calculate the soft-start capacitor value by using Equation 5. For the example circuit, the soft-start time is not too critical, because the output capacitor value is 3 × 47 µF, which does not require much current to charge to 5 V. The example circuit has the soft-start time set to an arbitrary value of 3.5 ms, which requires a 9.3-nF soft-start capacitor, as calculated by Equation 44. For this design, use the next-larger standard value of 10 nF.

Equation 43.

Equation 44.

8.2.2.8 Bootstrap Capacitor Selection

The TPS54561-Q1 device requires a 0.1-µF ceramic capacitor connected between the BOOT and SW pins for proper operation. The recommendation is a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or higher voltage rating.

8.2.2.9 Undervoltage Lockout Set Point

Using an external voltage divider on the EN pin of the TPS54561-Q1 device can adjust the undervoltage lockout (UVLO). The UVLO has two thresholds, one for power up when the input voltage is rising and the other for power down when the input voltage is falling. For the example design, the TPS54561-Q1 device should turn on and start switching once the input voltage increases above 6.5 V (UVLO start). After the regulator starts switching, it should continue to do so until the input voltage falls below 5 V (UVLO stop).

A resistor divider consisting of R_(UVLO1) and R_(UVLO2) between V_I and ground, and connected to the EN pin, can set programmable UVLO threshold voltage. Equation 3 and Equation 4 calculate the resistance values necessary. For the example application, a 442-kΩ resistor between V_I and EN (R1) and a 90.9-kΩ resistor between EN and ground (R2) are required to produce the 6.5-V start and 5-V stop voltages.

Equation 45.

Equation 46.

8.2.2.10 Output Voltage and Feedback Resistor Selection

The voltage divider of R5 and R6 sets the output voltage. For the example design, select 10.2 kΩ for R6. Use Equation 2 to calculate R5 as 53.55 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Because of the input current of the FB pin, the current flowing through the feedback network should be greater than 1 µA to maintain the output voltage accuracy. A value for R6 of less than 800 kΩ satisfies this requirement. Choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but may also introduce noise immunity problems.

Equation 47.

8.2.2.11 Compensation

There are several methods to design compensation for dc-dc regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Ignoring the slope compensation causes the actual crossover frequency to be lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole.

To get started, calculate the modulator pole, f_(P,mod), and the ESR zero, f_(Z,mod) using Equation 48 and Equation 49. For output capacitance C_(O), use a derated value of 87.4 µF. Use equations Equation 50 and Equation 51 to estimate a starting point for the crossover frequency, f_(CO). For the example design, f_(P,mod) is 1821 Hz and f_(Z,mod) is 1090 kHz. Equation 50 is the geometric mean of the modulator pole and the ESR zero, and Equation 51 is the geometric mean of modulator pole and half of the switching frequency. Equation 50 yields 44.6 kHz and Equation 51 gives 19.1 kHz. Use the geometric mean value of Equation 50 and Equation 51 for an initial crossover frequency which is 29.2 kHz. For this example, the target crossover frequency is 30 kHz for an improved transient response.

Next, calculate the compensation components. Use of a resistor in series with a capacitor creates a compensating zero. A capacitor in parallel with these two components forms the compensating pole.

Equation 48.

Equation 49.

Equation 50.

Equation 51.

To determine the compensation resistor, R4, use Equation 52. Assume the power stage transconductance, g_m(ps), is 17 S. The output voltage V_O, reference voltage V_ref, and amplifier transconductance g_m(ea), are 5 V, 0.8 V and 350 µS, respectively. Calculated the value for R4 as 16.84 kΩ, and then select a standard value of 16.9 kΩ. Use Equation 53 to set the compensation zero to the modulator pole frequency. Equation 53 yields 5172 pF for compensating capacitor C5. The selection for this design is 4700 pF.

Equation 52.

Equation 53.

If desired, implement a compensation pole by adding capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the compensation pole. The selected value of C8 is 47 pF for this example design.

Equation 54.

Equation 55.

8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary

With an input voltage of 12 V, the example design enters discontinuous-conduction mode when the output current is less than 408 mA. The power supply enters Eco-mode when the output current is lower than 25.3 mA. The input current draw is 257 µA with no load.

8.2.2.13 Power Dissipation Estimate

The following formulas show how to estimate the TPS54561-Q1 device power dissipation under continuous conduction mode (CCM) operation. These equations are not suitable if the device operates in discontinuous conduction mode (DCM).

The power dissipation of the IC includes conduction loss (P_(COND)), switching loss (P_(SW)), gate drive loss (P_(G)) and supply current loss (P_(Q)). Example calculations are shown with the 12-V nominal input voltage of the example design.

1. Conduction loss
Equation 56.
where
• I_O is the output current (A)
• r_DS(on) is the on-resistance of the high-side MOSFET (Ω)
• V_O is the output voltage (V)
• V_I is the input voltage (V)
2. Switching loss
Equation 57.
where
• f_(SW) is the switching frequency (Hz)
• t_r is the SW pin voltage rise time, estimated by t_r = V_DD (V) × 0.16 (ns/V) + 3 (ns)
3. Gate drive loss
Equation 58.
where
• Q_g is the total gate charge of the internal MOSFET
4. Quiescent current loss
Equation 59.
where
• I_Q is the operating nonswitching supply current

Therefore,

Equation 60.

For given T_A,

Equation 61.

where

• T_J is the junction temperature (°C)
• T_A is the ambient temperature (°C)
• R_θJA is the thermal resistance of the package (°C/W)
• P_(tot) is the total device power dissipation (W)

For given T_Jmax = 150°C

Equation 62.

where

• T_Amax is maximum ambient temperature (°C)
• T_Jmax is maximum junction temperature (°C)

Additional power losses occur in the regulator circuit because of the inductor ac and dc losses, the catch diode and PCB trace resistance. All of these losses impact the overall efficiency of the regulator.