7.3.1 Fixed Frequency PWM Control

The TPS54560B-Q1 uses fixed frequency, peak current mode control with adjustable switching frequency. The output voltage is compared through external resistors connected to the FB terminal to an internal voltage reference by an error amplifier. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output at the COMP terminal controls the high side power switch current. When the high side MOSFET switch current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP terminal voltage will increase and decrease as the output current increases and decreases. The device implements current limiting by clamping the COMP terminal voltage to a maximum level. The pulse skipping Eco-mode is implemented with a minimum voltage clamp on the COMP terminal.

7.3.2 Slope Compensation Output Current

The TPS54560B-Q1 adds a compensating ramp to the MOSFET switch current sense signal. This slope compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the high side switch is not affected by the slope compensation and remains constant over the full duty cycle range.

7.3.3 Pulse Skip Eco-mode

The TPS54560B-Q1 operates in a pulse skipping Eco-mode at light load currents to improve efficiency by reducing switching and gate drive losses. If the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The pulse skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of 600 mV.

When in Eco-mode, the COMP terminal voltage is clamped at 600 mV and the high side MOSFET is inhibited. Since the device is not switching, the output voltage begins to decay. The voltage control loop responds to the falling output voltage by increasing the COMP terminal voltage. The high side MOSFET is enabled and switching resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to the regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.

During Eco-mode operation, the TPS54560B-Q1 senses and controls peak switch current, not the average load current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor value. The circuit in Figure 33 enters Eco-mode at about 25.3 mA output current. As the load current approaches zero, the device enters a pulse skip mode during which it draws only 146 μA input quiescent current.

7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)

The TPS54560B-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW terminals provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended for stable performance over temperature and voltage.

When operating with a low voltage difference from input to output, the high side MOSFET of the TPS54560B-Q1 will operate at 100% duty cycle as long as the BOOT to SW terminal voltage is greater than 2.1 V. When the voltage from BOOT to SW drops below 2.1V, the high side MOSFET is turned off and an integrated low side MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low side MOSFET at high output voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V.

Since the gate drive current sourced from the BOOT capacitor is small, the high side MOSFET can remain on for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode voltage and the printed circuit board resistance.

Equation 1 calculates the minimum input voltage required to regulate the output voltage and ensure normal operation of the device. This calculation must include tolerance of the component specifications and the variation of these specifications at their maximum operating temperature in the application

Equation 1.

where

• V_F = Schottky diode forward voltage
• R_dc = DC resistance of inductor and PCB
• R_DS(on) = High-side MOSFET R_DS(on)

During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor is being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time required to recharge the BOOT capacitor is longer than the high side off time associated with cycle by cycle PWM control.

Equation 2 calculates the minimum input voltage required to regulate the output voltage and ensure proper operation of the device. This calculation must include tolerance of the component specifications and the variation of these specifications at their maximum operating temperature in the application

Equation 2.

where

• V_F = Schottky diode forward voltage
• R_DC = Total DC resistance of inductor and PCB
• R_DS(on) = High-side MOSFET resistance
• D = 0.99 effective duty cycle

At heavy loads, the minimum input voltage must be increased to ensure a monotonic startup. Equation 3 can be used to calculate the minimum input voltage for this condition.

Equation 3.

where

• D_(max) ≥ 0.9
• IB2SW = 100 µA
• TSW = 1 / Fsw
• VB2SW = VBOOT + VF
• VBOOT = (1.41 x V_IN - 0.554 - VF / TSW - 1.847 x 10³ x IB2SW) / (1.41 + 1 / Tsw)
• R_DS(on) = 1 / (-0.3 x VB2SW² + 3.577 x VB2SW - 4.246)

7.3.5 Error Amplifier

The TPS54560B-Q1 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier compares the FB terminal voltage to the lower of the internal soft-start voltage or the internal 0.8 V voltage reference. The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal soft-start voltage.

The frequency compensation components (capacitor, series resistor and capacitor) are connected between the error amplifier output COMP terminal and GND terminal.

7.3.6 Adjusting the Output Voltage

The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor divider from the output node to the FB terminal. It is recommended to use 1% tolerance or better divider resistors. Select the low side resistor R_LS for the desired divider current and use Equation 4 to calculate R_HS. To improve efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator will be more susceptible to noise and voltage errors from the FB input current may become noticeable.

Equation 4.

7.3.7 Enable and Adjusting Undervoltage Lockout

The TPS54560B-Q1 is enabled when the VIN terminal voltage rises above 4.3 V and the EN terminal voltage exceeds the enable threshold of 1.2 V. The TPS54560B-Q1 is disabled when the VIN terminal voltage falls below 4 V or when the EN terminal voltage is below 1.2 V. The EN terminal has an internal pull-up current source, I1, of 1.2 μA that enables operation of the TPS54560B-Q1 when the EN terminal floats.

If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 22 to adjust the input voltage UVLO with two external resistors. When the EN terminal voltage exceeds 1.2 V, an additional 3.4 μA of hysteresis current, I_HYS, is sourced out of the EN terminal. When the EN terminal is pulled below 1.2 V, the 3.4 μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use Equation 5 to calculate R_UVLO1 for the desired UVLO hysteresis voltage. Use Equation 6 to calculate R_UVLO2 for the desired VIN start voltage.

In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high input voltages (that is, from 40 V to 60 V), the EN terminal may experience a voltage greater than the absolute maximum voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using the EN resistors, the EN terminal is clamped internally with a 5.8 V zener diode that will sink up to 150 μA.

Figure 22. Adjustable Undervoltage Lockout (UVLO)

Figure 23. Low Input Voltages Applications

Equation 5.

Equation 6.

7.3.8 Internal Soft-Start

The TPS54560B-Q1 has an internal digital soft-start that ramps the reference voltage from zero volts to its final value in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 7.

Equation 7.

If the EN terminal is pulled below the stop threshold of 1.2 V, switching stops and the internal soft-start resets. The soft-start also resets in thermal shutdown.

7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK) Terminal)

The switching frequency of the TPS54560B-Q1 is adjustable over a wide range from 100 kHz to 2500 kHz by placing a resistor between the RT/CLK terminal and GND terminal. The RT/CLK terminal voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 8 or Equation 9 or the curves in Figure 5 and Figure 6. To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum controllable on time is typically 135 ns which limits the maximum operating frequency in applications with high input to output step down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. A more detailed discussion of the maximum switching frequency is provided in the next section.

Equation 8.

Equation 9.

7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency

The TPS54560B-Q1 implements peak current mode control in which the COMP terminal voltage controls the peak current of the high side MOSFET. A signal proportional to the high side switch current and the COMP terminal voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch current by driving the COMP terminal high. The error amplifier output is clamped internally at a level which sets the peak switch current limit. The TPS54560B-Q1 provides an accurate current limit threshold with a typical current limit delay of 60 ns. With smaller inductor values, the delay will result in a higher peak inductor current. The relationship between the inductor value and the peak inductor current is shown in Figure 24.

Figure 24. Current Limit Delay

To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54560B-Q1 implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB terminal voltage falls from 0.8 V to 0 V. The TPS54560B-Q1 uses a digital frequency foldback to enable synchronization to an external clock during normal start-up and fault conditions. During short-circuit events, the inductor current can exceed the peak current limit because of the high input voltage and the minimum controllable on time. When the output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The frequency foldback effectively increases the off time by increasing the period of the switching cycle providing more time for the inductor current to ramp down.

With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can be controlled by frequency foldback protection. Equation 11 calculates the maximum switching frequency at which the inductor current will remain under control when V_OUT is forced to V_OUT(SC). The selected operating frequency should not exceed the calculated value.

Equation 10 calculates the maximum switching frequency limitation set by the minimum controllable on time and the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to skip switching pulses to achieve the low duty cycle required at maximum input voltage.

Equation 10.

Equation 11.

where

• I_O — Output current
• I_CL — Current limit
• Rdc — inductor resistance
• V_IN — maximum input voltage
• V_OUT — output voltage
• V_OUTSC — output voltage during short
• Vd — diode voltage drop
• R_DS(on) — switch on resistance
• t_ON — controllable on time
• ƒ_DIV — frequency divide equals (1, 2, 4, or 8)

7.3.11 Synchronization to RT/CLK Terminal

The RT/CLK terminal can receive a frequency synchronization signal from an external system clock. To implement this synchronization feature connect a square wave to the RT/CLK terminal through either circuit network shown in Figure 25. The square wave applied to the RT/CLK terminal must switch lower than 0.5 V and higher than 1.7 V and have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising edge of the SW will be synchronized to the falling edge of RT/CLK terminal signal. The external synchronization circuit should be designed such that the default frequency set resistor is connected from the RT/CLK terminal to ground when the synchronization signal is off. When using a low impedance signal source, the frequency set resistor is connected in parallel with an ac coupling capacitor to a termination resistor (e.g., 50 Ω) as shown in Figure 25. The two resistors in series provide the default frequency setting resistance when the signal source is turned off. The sum of the resistance should set the switching frequency close to the external CLK frequency. It is recommended to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK terminal.

The first time the RT/CLK is pulled above the PLL threshold the TPS54560B-Q1 switches from the RT resistor free-running frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and the RT/CLK terminal becomes high impedance as the PLL starts to lock onto the external signal. The switching frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During the transition from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz and then increase or decrease to the resistor programmed frequency when the 0.5 V bias voltage is reapplied to the RT/CLK resistor.

The switching frequency is divided by 8, 4, 2, and 1 as the FB terminal voltage ramps from 0 to 0.8 volts. The device implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and fault conditions. Figure 26, Figure 27 and Figure 28 show the device synchronized to an external system clock in continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).

SPACER

Figure 25. Synchronizing to a System Clock

Figure 26. Plot of Synchronizing in CCM

Figure 28. Plot of Synchronizing in Eco-mode

Figure 27. Plot of Synchronizing in DCM

7.3.12 Overvoltage Protection

The TPS54560B-Q1 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients in designs with low output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the FB terminal voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak current limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier output transitions to the normal operating level. In some applications, the power supply output voltage can increase faster than the response of the error amplifier output resulting in an output overshoot.

The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB terminal voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB terminal voltage is greater than the rising OVP threshold, the high side MOSFET is immediately disabled to minimize output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the internal voltage reference, the high side MOSFET resumes normal operation.

7.3.13 Thermal Shutdown

The TPS54560B-Q1 provides an internal thermal shutdown to protect the device when the junction temperature exceeds 176°C. The high side MOSFET stops switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature falls below 164°C, the device reinitiates the power up sequence controlled by the internal soft-start circuitry.

7.3.14 Small Signal Model for Loop Response

Figure 29 shows an equivalent model for the TPS54560B-Q1 control loop which can be simulated to check the frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm_EA of 350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor R_o and capacitor C_o model the open loop gain and frequency response of the amplifier. The 1mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small signal response of the overall loop. The dynamic loop response can be evaluated by replacing R_L with a current source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is only valid for continuous conduction mode (CCM) operation.

Figure 29. Small Signal Model for Loop Response

7.3.15 Simple Small Signal Model for Peak Current Mode Control

Figure 30 describes a simple small signal model that can be used to design the frequency compensation. The TPS54560B-Q1 power stage can be approximated by a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 12 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP terminal voltage (node c in Figure 29) is the power stage transconductance, gm_PS. The gm_PS for the TPS54560B-Q1 is 17 A/V. The low-frequency gain of the power stage is the product of the transconductance and the load resistance as shown in Equation 13.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 14). The combined effect is highlighted by the dashed line in the right half of Figure 30. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same with varying load conditions. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 15).

Figure 30. Simple Small Signal Model and Frequency Response for Peak Current Mode Control

Equation 12.

Equation 13.

Equation 14.

Equation 15.

7.3.16 Small Signal Model for Frequency Compensation

The TPS54560B-Q1 uses a transconductance amplifier for the error amplifier and supports three of the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 31. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors. Equation 16 and Equation 17 relate the frequency response of the amplifier to the small signal model in Figure 31. The open-loop gain and bandwidth are modeled using the R_O and C_O shown in Figure 31. See the application section for a design example using a Type 2A network with a low ESR output capacitor.

Equation 16 through Equation 25 are provided as a reference. An alternative is to use WEBENCH software tools to create a design based on the power supply requirements.

Figure 31. Types of Frequency Compensation

Figure 32. Frequency Response of the Type 2A and Type 2B Frequency Compensation

Equation 16.

Equation 17.

Equation 18.

Equation 19.

Equation 20.

Equation 21.

Equation 22.

Equation 23.

Equation 24.

Equation 25.

7.4.1 Operation with V_IN < 4.5 V (Minimum V_IN)

The device is recommended to operate with input voltages above 4.5 V. The typical VIN UVLO threshold is 4.3 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage, the device will not switch. If EN is externally pulled up to V_IN or left floating, when V_IN passes the UVLO threshold the device will become active. Switching is enabled the soft start sequence is initiated. The TPS54560B-Q1 will start at the soft start time determined by the internal soft start time.

7.4.2 Operation with EN Control

The enable threshold voltage is 1.2 V typical. With EN held below that voltage the device is disabled and switching is inhibited even if V_IN is above its UVLO threshold. The IC quiescent current is reduced in this state. If the EN voltage is increased above the threshold while V_IN is above its UVLO threshold, the device becomes active. Switching is enabled, and the soft start sequence is initiated. The TPS54560B-Q1 will start at the soft start time determined by the internal soft start time.