8.3.1 Dynamic Rectifier Control

The Dynamic Rectifier Control algorithm offers the end-system designer optimal transient response for a given maximum output current setting. This is achieved by providing enough voltage headroom across the internal regulator (LDO) at light loads in order to maintain regulation during a load transient. The WPC system has a relatively slow global feedback loop where it can take up to 150 ms to converge on a new rectifier voltage target. Therefore, a transient response depends on the loosely-coupled transformer's output-impedance profile. The Dynamic Rectifier Control allows for a 1.5-V change in rectified voltage before the transient response is observed at the output of the internal regulator (output of the bq51025 device). A 1-A application allows up to a 2-Ω output impedance. Figure 13 shows the Dynamic Rectifier Control behavior during active power transfer.

8.3.2 Dynamic Power Scaling

The Dynamic Power Scaling feature allows for the loss characteristics of the bq51025 device to be scaled based on the maximum expected output power in the end application. This effectively optimizes the efficiency for each application. This feature is achieved by scaling the loss of the internal LDO based on a percentage of the maximum output current. Note that the maximum output current is set by the K_ILIM term and the R_ILIM resistance (where R_ILIM = K_ILIM / I_ILIM). The flow diagram in Figure 13 shows how the rectifier is dynamically controlled (Dynamic Rectifier Control) based on the voltage level at the ILIM pin (V_ILIM). This voltage represents a fixed percentage of the I_ILIM setting. Table 1 summarizes how the rectifier behavior is dynamically adjusted based on two different R_ILIM settings. Table 1 is shown for I_MAX, which is the maximum operating output current and is typically lower than I_ILIM (about 20% lower). See RILIM Calculations for more details on how to set I_ILIM.

Table 1 shows the shift in the Dynamic Rectifier Control behavior based on the two different R_ILIM settings. With the rectifier voltage (V_RECT) as the input to the internal LDO, this adjustment in the Dynamic Rectifier Control thresholds dynamically adjusts the power dissipation across the LDO where,

Equation 1.

Figure 22 shows how the Dynamic Power Scaling feature reduces the V_RECT with increased load, allowing the post-regulation LDO to have maximum headroom at low load conditions for better load transient performance and minimal power dissipation at high loads. Note that this feature balances efficiency with optimal system transient response.

8.3.3 VO_REG Calculations

The bq51025 device allows the designer to set the output voltage by setting a feedback resistor divider network from the OUT pin to the VO_REG pin, as seen in Figure 7. Select the resistor divider network so that the voltage at the VO_REG pin is 0.5 V (default setting) at the desired output voltage. The target VO_REG voltage can be changed through I²C by changing Table 4

Figure 7. VO_REG Network

Choose the desired output voltage V_OUT and R₆:

Equation 2.

Equation 3.

8.3.4 RILIM Calculations

The bq51025 device includes a means of providing hardware overcurrent protection (I_ILIM) through an analog current regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum allowable output current (for example, current compliance). The R_ILIM resistor size also sets the thresholds for the dynamic rectifier levels providing efficiency tuning per each application’s maximum system current. The calculation for the total R_ILIM resistance is as follows:

Equation 4.

Equation 5.

The R_ILIM allows for the ILIM pin to reach 1.2 V when operating in proprietary mode (up to 10-W output power) when the output current is equal to I_ILIM. When the receiver operates in standard WPC low-power mode, the ILIM pin voltage threshold is changed from 1.2 to 0.6 V, setting the low-power mode current limit to half of that at the proprietary mode setting.

In the case where having the current limit change by a factor of two between modes is not desired, the two current limit levels may be independently controlled in two ways:

• By programming the IO_REG level through I²C
• By changing the effective R_ILIM value for each mode by using an external switch controlled by the PMODE pin

To adjust the current limit for each mode through I²C, R_ILIM is chosen using Equation 4 where I_ILIM is the current limit for proprietary mode (that is, higher current setting). The host should first set the desired current limit value for low-power mode as a percentage of I_ILIM through the IO_REG bits and then disable the 2X current scaling by setting the I2C_ILIM bit in Table 5 and Table 6 respectively to enable programmability. By default, IO_REG is set to the highest current setting allowed by R_ILIM (that is, 100% of I_ILIM).

If I²C control is not available, the current limit for low power and proprietary modes can be set independently by shorting a portion of the R₁ resistance using an external switch as shown in Figure 8. R_ILIM is calculated using Equation 4, where I_ILIM is the desired current limit for proprietary mode. The resistance to set the current limit in low-power mode, R_{ILIM_LP} is calculated by Equation 6.

Equation 6.

where

The value for R_{1_A} is given by R_{ILIM_LP} – R_FOD. The value of R_{1_B} is then R_ILIM – R_{1_A} – R_FOD. Note that with this method I_ILIM must be less than 2 × I_{ILIM_LP}

Figure 8. Current Limit Setting for bq51025 Using External Switch

When choosing I_ILIM, consider the following two possible operating conditions:

• If the user's application requires an output current equal to or greater than the external I_ILIM that the circuit is designed for (input current limit on the charger where the receiver device is tied higher than the external I_ILIM), ensure that the downstream charger is capable of regulating the voltage of the input into which the receiver device output is tied to by lowering the amount of current being drawn. This ensures that the receiver output does not drop to zero. Such behavior is referred to as VIN DPM in TI chargers. Unless such behavior is enabled on the charger, the charger pulls the output of the receiver device to ground when the receiver device enters current regulation.
• If the user's applications are designed to extract less than the I_ILIM, typical designs should leave a design margin of at least 10%, so that the voltage at ILIM pin reaches 1.2 V when 10% more than maximum current is drawn from the output. Such a design would have input current limit on the charger lower than the external ILIM of the receiver device.

However, in both cases, the charger must be capable of regulating the current drawn from the device to allow the output voltage to stay at a reasonable value. This same behavior is also necessary during the WPC communication. The following calculations show how such a design is achieved:

Equation 7.

Equation 8.

where

When referring to the application diagram shown in Typical Applications, R_ILIM is the sum of the R₁ and R_FOD resistance (that is, the total resistance from the ILIM pin to GND). R_FOD is chosen according to the application. To obtain the tool for calculating R_FOD, contact your TI representative. Use R_FOD to allow the receiver implementation to comply with WPC v1.2 requirements related to received power accuracy.

8.3.5 Adapter Enable Functionality

The bq51025 device can also help manage the multiplexing of adapter power to the output and can shut off the TX when the adapter is plugged in and is above the V_AD-EN. After the adapter is plugged in and the output turns off, the RX device sends an EPT to the TX. In this case, the AD_EN pins are then pulled to approximately 4 V below AD, which allows the device to turn on the back-to-back PMOS connected between AD and OUT (see Figure 32).

Both the AD and AD-EN pins are rated at 30 V, while the OUT pin is rated at 20 V. Note that it is required to connect a back-to-back PMOS between AD and OUT so that voltage is blocked in both directions. Also, when AD mode is enabled, no load can be pulled from the RECT pin because this could cause an internal device overvoltage in the bq51025 device.

8.3.6 Turning Off the Transmitter

The WPC v1.2 specification allows the receiver to turn off the transmitter and put the system in a low-power standby mode. There are two different ways to accomplish this with the bq51025 device. The EPT charge complete (WPC) can be sent to the TX by pulling the TS pin high (above 1.4 V). The bq51025 device will then sense this and send the appropriate signal to the TX, thus putting the TX in a low-power standby mode.

8.3.7 Communication Current Limit

Communication current limit is a feature that allows for error-free communication to happen between the RX and TX in the WPC mode. This is done by decoupling the coil from the load transients by limiting the output current during communication with the TX. The communication current limit is set according to Table 3. The communication current limit can be enabled by pulling CM_ILIM pin low or disabled by pulling the CM_ILIM pin high (>1.4 V) . An internal pulldown enables communication current limit when the CM_ILIM pin is left floating.

When the communication current limit is enabled, the amount of current that the load can draw is limited. If the charger in the system does not have a VIN-DPM feature, the output of the receiver collapses if communication current limit is enabled. Please note that power dissipation within the device will increase during current limiting, lowering overall system efficiency. To disable communication current limit, pull CM_ILIM pin high.

8.3.8 PD_DET and TMEM

PD_DET is an open-drain pin that goes low based on the voltage of the TMEM pin. When the voltage of TMEM is higher than 1.6 V, PD_DET is low. The voltage on the TMEM pin depends on capturing the energy from the digital ping from the transmitter and storing it on the C₅ capacitor in Figure 9. After the receiver sends an EPT (charge complete), the transmitter shuts down and goes into a low-power mode. However, it continues to check if the receiver would like to renegotiate a power transfer by periodically performing the digital ping. The energy from the digital ping can be stored on the TMEM pin until the next digital ping refreshes the capacitor. The designer can choose a bleedoff resistor, R_MEM, in parallel with C₅ that sets the time constant so that the TMEM pin will fall below 1.6 V once the next ping timer expires. The duration between digital pings is indeterminate and depends on each transmitter manufacturer.

Figure 9. TMEM Configuration

Set capacitor on C₅ = TMEM to 2.2 µF. Resistor R_MEM across C₅ can be set by understanding the duration between digital pings (t_ping). Set the resistor such that:

Equation 9.

PD_DET typically requires a pullup resistor to an external source. A higher current through the PD_DET pin may affect the output regulation of the device. To improve regulation, TI recommends pullup resistor values in the range of 15 to 100 kΩ.

8.3.9 TS/CTRL

The bq51025 device includes a ratiometric external temperature sense function. The temperature sense function has a low ratiometric threshold which represents a hot condition. TI recommends an external temperature sensor to provide safe operating conditions for the receiver product. This pin is best used for monitoring the surface that can be exposed to the end user (for example, place the negative temperature coefficient (NTC) resistor closest to the user touch point on the back cover). A resistor in series or parallel can be inserted to adjust the NTC to match the trip point of the device. The implementation in Figure 10 shows the series-parallel resistor implementation for setting the threshold at which V_TS-HOT is reached. When the V_TS-HOT threshold is reached, the device will send an EPT – overtemperature signal for a WPC transmitter.

Figure 10. NTC Resistor Setup

Figure 10 shows a parallel resistor setup that can be used to adjust the trip point of V_TS-HOT. After the NTC is chosen and R_NTCHOT at V_TS-HOT is determined from the data sheet of the NTC, use Equation 10 to calculate R₁ and R₃. In many cases, depending on the NTC resistor, R₁ or R₃ can be omitted. To omit R₁, set R₁ to 0, and to omit R₃, set R₃ to 10 MΩ in the calculation.

Equation 10.

8.3.10 PMODE Pin

Connect a 5-MΩ resistor to ground in order to use PMODE to indicate the receiver mode of operation. PMODE is high when in low-power mode and low in proprietary mode. This pin may be used to control the gate of an NMOS switch to change the R_ILIM, and hence, the current limit based on the maximum power allowed by the transmitter (10 W for bq500215, 5 W or less otherwise). This pin may be left floating if not used. and show the PMODE behavior during startup.

8.3.11 I²C Communication

The bq51025 device allows for I²C communication with the internal CPU. The I²C address for the device is 0x6C. In case the I²C is not used, ground SCL and SDA. See Register Maps for more information.

8.3.12 Input Overvoltage

If the input voltage suddenly increases in potential for some condition (for example, a change in position of the equipment on the charging pad), the voltage-control loop inside the bq51025 device becomes active, and prevents the output from going beyond V_OUT(REG). The receiver then starts sending back error packets every 32 ms until the input voltage comes back to an acceptable level, and then maintains the error communication every 250 ms.

If the input voltage increases in potential beyond V_{RECT_OVP}, the device switches off the LDO and informs the primary to terminate power. In addition, a proprietary voltage protection circuit is activated by means of C_CLAMP1 and C_CLAMP2 that protects the device from voltages beyond the maximum rating of the device.

8.3.13 Alignment Aid Using Frequency Information

The bq51025 device provides the host through I²C with power signal frequency information that would enable it to determine the optimal alignment position on the charging surface of a frequency-controlled transmitter. For these WPC transmitters, the power signal frequency increases as the coupling between the primary and secondary coils increases. By finding the position in the charging pad that has the highest frequency, the host can determine that the best possible alignment with the transmitter coil has been achieved.

The bq51025 continuously stores a measurement of the power signal frequency in I²C register 0xFB to provide the host the information it needs to determine optimal placement. The power signal frequency is given by:

Equation 11.

where

Figure 11 shows the expected register values across the frequency range.

Figure 11. I²C Code vs Power Signal Frequency

8.5.1 Wireless Power Supply Current Register 1

8.5.2 Wireless Power Supply Current Register 2

8.5.3 Wireless Power Supply Current Register 3

8.5.4 I²C Mailbox Register

8.5.5 I²C Mailbox Register 2

8.5.6 I²C Mailbox Register 3

8.5.7 Wireless Power Supply FOD RAM

8.5.8 Wireless Power User Header RAM

8.5.9 Wireless Power USER V_RECT Status RAM

8.5.10 Wireless Power V_OUT Status RAM

8.5.11 Wireless Power Proprietary Mode REC PWR MSByte Status RAM

8.5.12 Wireless Power REC PWR LSByte Status RAM

8.5.13 Wireless Power Prop Packet Payload RAM Byte 0

8.5.14 Wireless Power Prop Packet Payload RAM Byte 1

8.5.15 Wireless Power Prop Packet Payload RAM Byte 2

8.5.16 Wireless Power Prop Packet Payload RAM Byte 3