Table 1. Design Parameters

9.2.2.1 Auxiliary Supply Voltage

The 9.2-V minimum requirement of the UC1825 and 20-V gate-source maximum of the mosfets imply an approximate range from 10 V to 18 V of inputs. The 10-V value was selected to supply both VCC and VC (totem pole outputs) while keeping power dissipation in the IC low. The circuit used is a simple resistor-Zener dissipative network with ample bypassing capacitors located near the IC to reduce noise. The oscillator frequency selected is 1.5 MHz, thus resulting in a 670-ns period.

Oscillator frequency versus Rt, Ct, and deadtime curves:

• F0 = 1.5 MHz
• T period = 670 ns
• Cl = 470 pF
• Rt = 1.5 K

Therefore;

• T (on) = 570 ns (maximum)
• T (off) = 100 ns (minimum) DUTY CYCLE
• d max = T (on) max = 570 ns = 85% T (period) 670 ns

9.2.2.2 Oscillator Frequency

The oscillator frequency selected is 1.5 MHz, resulting in a 670-ns period. For these equations, oscillator frequency versus Rt, Ct, and deadtime curves:

• F₀ = 1.5 MHz; T period = 670 ns
• C_l = 470 pF
• R_t = 1.5 K

Therefore;

• T (on) = 570 ns (maximum)
• T (on) = 570 ns (maximum)
Equation 3.

9.2.2.3 Preliminary Considerations

Before designing the main transformer, several parameters must be defined and determined. Standard design procedures are used for this first-cut approximation.

9.2.2.4 Input Power

Equation 4.

Let n = 75% for a 5 V, single output power supply.

Equation 5.

9.2.2.5 Primary Current

The primary current can be approximated using the low-line constraints of 42-V DC as shown in Equation 6:

Equation 6.

The primary current during the transistor on time is calculated by Equation 7:

Equation 7.

The RMS primary current is calculated by Equation 8:

Equation 8.

9.2.2.6 Sense Resistor R(s)

Primary current is sensed and controlled in a current mode controller by first developing a voltage proportional to the primary current, used as an input to UC1825A-SP. This is accomplished by sense resistor R(s) with a calculated value of the I limit threshold value divided by the primary current at the desired current limit point, typically 120% I (maximum) shown in Equation 9.

Equation 9.

9.2.2.7 MOSFET DC Losses

A high-quality mosfet is used to keep both DC and switching losses low, with an R(ds) on max of 0.8 Ω (see Equation 10 to Equation 13). Calculation of the voltage drops across the device are required for the transformer design.

During an overload:

9.2.2.8 Selection of Core Material

Few manufacturers provide core loss curves for frequencies above 500 khz. To minimize power dissipation in the core, the flux density must be drastically reduced in comparison to the 20 kHz to 150 kHz versions. Typical operation is at a total flux density swing, delta B, of 0.030 Tesla (300 Gauss) while approaching the 1 MHz region. TDK’s H7C4 material was selected for it’s low loss, high frequency characteristics.

9.2.2.9 Main Transformer Design

The first step in transformer design is to determine the preliminary turns ratio. Once obtained, the minimum cross-sectional area core (Ae) can be calculated, and core selection made possible.

9.2.2.10 Calculation of Transformer

Voltages and Turns Ratio is calculated by Equation 14 through Equation 19.

Equation 19.

The secondary is designed for excellent coupling using copper foil, and the primary has been rounded to the nearest lower turns (see Equation 20).

The actual number of both primary and secondary turns will be determined by the ferrite core characteristics as a function of operating frequency and Gauss level.

9.2.2.11 Minimum Core Size

The minimum cross-sectional area core that can be used is calculated with Equation 21 for core loss limited applications.

Equation 21.

At first it would seem that the core area required for this 1.5-MHz switcher would be ten times smaller than that of a 150-kHz version. This would be true if the flux density, number of turns and core losses remained constant. However, losses are a function of frequency, and as frequency increases, the flux density swing (Delta B) must be drastically reduced to provide a similar core loss, hence temperature rise. In this example, an acceptable figure was selected of one percent of the total output power, or one-half watt. Empirically, this translates to a temperature rise of 25°C, at 325 Gauss (0.0325 Tesla) for cores with a cross-sectional area of 0.70 cm², a ballpark estimate of the true core size. This formula can be rewritten as Equation 22:

Equation 22.

Equation 22 is a more convenient formula because the right hand side of the equation contains all constants. Input voltage, frequency of operation and flux density have already been determined. The selection of core size (cross-sectional area) is inversely proportional to the number of primary turns, and conversely. Based on the five-to-one turns ratio, an original assumption of five turns for the primary would result in a large core size for this 50-W application. Alternatively, a ten turn primary is used to minimize core size.

Substituting previous values for high line operation at 0.0325 Tesla (325 Gauss) and a magnetic operating frequency of 750 kHz is calculated by Equation 23:

Equation 23.

9.2.2.12 Core Loss Limited Conditions

As the switching frequencies are increased, generally a reduction of core size or minimum number of turns is realized. This is true, however, but only to the point at which the increasing core losses prevent a further reduction of either size or minimum turns. This crossover point occurs at different frequencies for each individual ferrite material based upon their losses and acceptable circuit losses, or temperature rise.

9.2.2.13 Core Geometry Selection

A variety of standard core shapes are available in the cross-sectional area range of 0.62 cm² to 0.84 cm² (see Table 2). Considerations of safety agency spacing requirements, physical dimensions, window area and relative cost of assembly must be evaluated.

The LP 22/13 style was selected to easily terminate (breakout) the high current output windings. For a given cross-sectional area, it occupies less PC board space, and has good shielding characteristics.

9.2.2.14 Wire Size Selection

The single, most difficult task in high frequency magnetic design is to minimize the eddy current losses, or skin effects while optimizing wire sizes. Penetration depth refers to the thickness (or depth) into a copper conductor in which a wave will penetrate for a specific frequency. For copper at 100°C, use Equation 24:

At 750 kHz, this corresponds to 8.66 × 103 cm, or about the thickness of an AWG #39 wire. Larger size wire can be used, however the AC current flows only in the depth penetrated at the switching frequency.

For low current windings, several strands of thin wire can be paralleled, or twisted together forming a bundle. Seven wires twisted around each other closely approximate a round conductor with a net diameter of three times the individual wire diameter. This twisting is commonly done at 10-12 turns per foot, and significantly reduces parasitics between wires at high frequencies.

Medium to high current windings require the use of Litz wire, a similar bundle of numerous conductors. Copper foil is also an excellent choice.

Industry practice is to operate at 450-A (RMS) per centimeter squared, or 2.22 × 10^–3 cm²/A, which applies to windings operating at an acceptable temperature rise (see Equation 25 through Equation 31).

9.2.2.15 Calculate Secondary RMS Current

Equation 27.

Equation 28.

Figure 17. 7 Conductors

For a given bundle of 7 conductors as shown in Figure 17, the cross-sectional area of each conductor can be calculated by Equation 32:

Equation 32.

The cross-sectional area of an AWG 36 wire is 1.32 × 10^–4; therefore, three bundles of seven conductors each must be used. Two bundles were used as a compromise between practical winding considerations and acceptable eddy current losses.

Copper foil is used for the secondary, with a required width slightly less than the bobbin width, and thickness determined by Equation 33:

Equation 33.

This corresponds to 0.003” thick foil, a standard value. In practice, slightly thicker foil (0.004” to 0.005”) may be required to minimize power losses in the transformer.

9.2.2.16 Transformer Assembly

Standard practice to increase coupling between primary and secondary is position both as closely as possible to each other inside the transformer. In this design, the first layer wound is one primary, and the next layer is the corresponding secondary. This is again followed by the other secondary and primary. It is important to keep the secondaries in close proximity because both will be conducting simultaneously twice per period. The primaries do not conduct in this manner, so coupling from primary A to primary B is not critical, only primary A to secondary C, and primary B to secondary D.

Referring to Figure 18, primary A is wound closest to the bobbin. After insulation, secondaries C and D are wound bifilar and insulated (see Figure 19). Primary B is wound last, then terminated so that primaries A and B are wired in series, likewise for secondaries C and D.

Figure 18. Transformer Schematic

Figure 19. Transformer – Exploded View

9.2.2.17 Calculation of Winding Resistances and Losses

The mean length of turn for the bobbin can be determined from the specifications of O.D. and I.D., and for the BLP 22/13 a figure of 4.51 cm or 1.77 inches was obtained. AWG #36 wire has a resistance of 1.82 × 10^–2 Ω/cm at 100°C for the following:

Primary resistance can be calculated by Equation 34:

Equation 34.

Voltage drop and power loss in each half winding can also be calculated by Equation 35 through Equation 37:

The resistance of the secondary can be approximated by using the wire tables, and substituting the foil for wire of similar cross-sectional area. In this example, AWG #16 wire is used to obtain Rsec = 1.58 × 10^-4 Ω/cm.

Equation 40.

9.2.2.18 Transformer Power Losses

The total copper losses for two windings are then calculated by Equation 42:

Estimated eddy current losses are approximately 50% of the copper losses. Pcu ≈ 0.50 W.

Given the core material type, geometry, frequency and operating Gauss level, the ferrite losses can be calculated. From the manufacturers information, the typical loss coefficient for H7C4 material operating at a flux density swing of 0.035 Tesla (350 Gauss) at 750 kHz is 0.15 W per cubic centimeter of core volume, which is 3.327 cm³ per LP 22/13 core set; therefore Equation 43:

The total power lost is a summation of the copper and ferrite losses calculated by Equation 44:

9.2.2.19 Output Section

9.2.2.19.1 Output Choke Calculations

Typically, the RMS output ripple current is less than 15% Idc, or 1.5 A in this case. Delta I, the peak-to-peak ripple therefore is twice the RMS, or 3 A as calculated by Equation 45.

Equation 45.

Due to the small value of inductance required, the conventional approach will not be used. Instead, a simple RF type wound coil will be designed using the solenoid equation found in most reference texts. A thick pencil will be used as the coil form with a diameter of 0.425 inches; however, any similar item will suffice.

The form factor, F, is a function of the form diameter divided by the length of the wound coil, or D/L (see Equation 46). A few gyrations will take place before the exact values are obtained; however, this goes quickly. The form factor is listed in Table 3 for various practical values of D/L.

Table 3. Form Factor

COIL DIAMETER, LENGTH	FORM FACTOR F
0.1	0.0025
0.25	0.0054
0.5	0.01
1	0.0173
2	0.026
5	0.04

Equation 46. L(µH) = F × N² × D(inches), N = (L/F × D)¹ (turns)

where

• D = 0.425
• D/L = 1 (approximately)
• F = 0.0173
• N = (0.690 / 0.0173 × 0.425)¹² = 9.76 turns

Rounding off to the nearest next number of turns the actual inductance for 10 turns can be calculated by Equation 47:

Equation 47. L(µH) = 0.0173 × 10² × 0.425 = 744 nH

In an air core inductor, the permeability u equals unity; therefore, the flux density B equals the driving function H.

9.2.2.19.2 Output Capacitor

Equation 48.

Equation 49. C = Q / dV

where

• dV (output ripple) equals 0.1 V.

Equation 50. C = Ip-p / 8 × F × dV = 3/8 × 1.5 × 10⁶ × 0.1 = 2.5 µF

Three 1-µF capacitors are used in parallel. With a typical ripple voltage of approximately 50 mV due to ESR, the ESR each (at 1.5 mHz) must be approximately 150 mΩ. The Unitrode ceramic monolithic capacitor series was selected for their excellent high frequency characteristics.

Resonance, and its effect at these frequencies must be taken into account. In this case, the capacitor reaches resonance at 1.5 mHz, and the effective impedance is resistive.

9.2.2.20 UC1825A-SP PWM Control Section

9.2.2.20.3 Slope Compensation

Slope compensation is required to compensate for the peak to average differences in primary current as a function of pulse width. Adding a minimum of 50% of the reflected downslope of the output current waveform to the primary current is required. See the Unitrode application note A New Integrated Circuit for Current Mode Control (SLUA075) and the Unitrode application note Modelling, Analysis and Compensation of the Current-Mode Converter (SLUA101) for further information. Empirically, 60-75% must be used to accommodate circuit tolerances and increase stability5 Resistors R2 and R4 in this circuit form a voltage divider from the oscillator output to the RAMP input, superimposing the slope compensation on the primary current waveform. Capacitor C6 is an AC coupling capacitor, and allows the 1.8-V swing of the oscillator to be used without adding offset circuitry. Capacitor C7 has a two-fold purpose. During turnon it filters the leading edge noise of the current waveform, and provides a negative going pulse across R4 to the ramp input at the end of each cycle. This overrides any parasitic capacitance at the ramp input, (pin 7) that would tend to hold it above 0 V. This insures the proper voltage input at the beginning of the next cycle.

Figure 20. Slope Compensation Steps

For the purposes of determining the resistor values, capacitors C4 (timing), C6 (ac coupling) and C7 (filtering) can be removed from the circuit schematic. The simplified model represented in Figure 21 is used for the calculations in Equation 51 through Equation 61. These calculations can be applied to all current-mode circuits using a similar scheme.

Figure 21. Slope Compensation Steps

• STEP 1. Calculate Inductor Downslope:
Equation 51. S_L' = di/dt = Vsec / L = 5.9 V / 0.740 pH = 8 A/µS
• STEP 2: Calculate Inductor Downslope:
Equation 52. S_L' = S_L' / N (turns ratio) = 8/5 = 1.6 A/µS
• STEP 3: Calculate Equivalent Ramp Downslope Voltage:
Equation 53. V S_L' = S_L' × Rsense = 1.6 × 0.375 = 0.600 V/µS
• STEP 4: Calculate Oscillator Slope:
Equation 54. VS(osc) = d(V_osc) / T on = 1.8 V / 570 ns = 3.15 V/µS
• STEP 5: Generate the Ramp Equations: Using superpostion, the circuit can be configured as shown in Figure 22.
Figure 22. Slope Compensation Steps
Equation 55.

Substituting

Equation 56. V(ramp) = VS(L) + VS(comp)

Where

Equation 57.
• STEP 6: Calculate Slope Compensation:
Equation 58. VS(comp) = m × S(L)
where
• m equals the amount of inductor to be introduced.
Equation 59.

Solving for R2:

Equation 60.

Using Circuit Values:

Equation 61. R2 = 7.05 × R4

For simplicity, let R4 equal 1 kΩ and R2 therefore equals 7.05 K. Using the nearest standard value resistor of
6.8 K, the exact amount of downslope is minimally affected. It is important that the series combination of R2 and R4 is high enough in resistance not to load down the oscillator and cause frequency shifting.

9.2.2.21 Closing the Feedback Loop

9.2.2.21.2 Control to Output Gain

The control to output gain will vary with output loading, and as the load is increased the gain decreases. Output capacitor ESR will determine the frequency at which the zero occurs, thus changing the gain as a function of ESR. To ensure stability through all combinations of load and ESR, the amplifier will be compensated to cross zero db at approximately one-fifth of the switching frequency with ample phase margin.

The output filter pole and zero occur at:

Equation 62. F_p = 1/2 π R(load) C(output)

Equation 63. F_p = 1/2 π R (esr) C (output)

Circuit Parameters:

Equation 64. C (output) = 3 pF; ESR (each) = 0.050 min – 0.300 max

For three capacitors in parallel:

Equation 65. ESR = 0.016 – 0.100 Ω

Equation 66. R(output) = 2.5 Ω at 2 A, 0.5 Ω at 10 A

Using the previous Equations:

Equation 67. F_p (2 A) = 1 / (2 × 3.14 × 2.5 × 3 × 10^-6) = 21.2 kHz

Equation 68. F_p (10 A) = 1 / (2 × 3.14 × 0.5 × 3 × 10^-6) = 106.1 kHz

Equation 69. F_p (high) = 1 / (2 × 3.14 × 0.016 × 3 × 10^-6) = 3.315 mHz

Equation 70. F_Z(low) = 1 / (2 × 3.14 × 0.100 × 3 × 10^-6) = 530.5 kHz

Gain:

Equation 71.

Therefore, at 2 A and 10 A:

Equation 72. V_o / V_c = K × ro = 11.76 × 2.5 = 29.4 db (2A)

Equation 73. V_o / V_c = K × ro = 11.76 × 0.5 = 15.4 db

9.2.2.22 Summary

The demands of higher power densities will undoubtedly throttle many switch-mode power supply designs into and beyond the megahertz region in the near future. Designers will be facing the challenges of selecting switching devices, magnetic materials and IC controllers built exclusively for high efficiency at these frequencies. The thrust from contemporary hundreds of kHz designs to MHz versions is rapidly making progress. This
1.5-MHz current mode push-pull is an example of what can successfully be accomplished with existing high speed components and technology.

Figure 23. UC1825A-SP Block Diagram