9.3.1 Open-Circuit Detection

The TLC59108 LED open-circuit detection compares the effective current level I_OUT with the open load detection threshold current I_{OUT, Th}. If I_OUT is below the threshold I_{OUT, Th} the TLC59108 detects an open load condition. This error status can be read out as an error flag through the EFLAG register.

For open-circuit error detection, a channel must be on.

9.3.2 Overtemperature Detection and Shutdown

The TLC59108 LED is equipped with a global overtemperature sensor and eight individual channel-selective overtemperature sensors.

• When the global sensor reaches the trip temperature, all output channels are shutdown, and the error status is stored in the internal Error Status register of every channel. After shutdown, the channels automatically restart after cooling down, if the control signal (output latch) remains on. The stored error status is not reset after cooling down and can be read out as the error status code in the EFLAG register.
• When one of the channel-specific sensors reaches trip temperature, only the affected output channel is shut down, and the error status is stored only in the internal Error Status register of the affected channel. After shutdown, the channel automatically restarts after cooling down, if the control signal (output latch) remains on. The stored error status is not reset after cooling down and can be read out as error status code in the EFLAG register.

For channel-specific overtemperature error detection, a channel must be on.

The error flags of open-circuit and overtemperature are ORed to set the EFLAG register.

The error status code due to overtemperature is reset when the host writes 1 to bit 7 of the MODE2 register. The host must write 0 to bit 7 of the MODE2 register to enable the overtemperature error flag.

9.3.3 Power-On Reset

When power is applied to V_CC, an internal power-on reset holds the TLC59108 in a reset condition until V_CC reaches V_POR. At this point, the reset condition is released and the TLC59108 registers, and I²C bus state machine are initialized to their default states (all zeroes), causing all the channels to be deselected. Thereafter, V_CC must be lowered below 0.2 V to reset the device.

9.3.4 External Reset

A reset can be accomplished by holding the RESET pin low for a minimum of t_W. The TLC59108 registers and I²C state machine are held in their default states until the RESET input is again high.

This input requires a pullup resistor to V_CC if no active connection is used.

9.3.5 Software Reset

The Software Reset Call (SWRST Call) allows all the devices in the I²C bus to be reset to the power-up state value through a specific I²C bus command. To be performed correctly, the I²C bus must be functional and there must be no device hanging the bus.

The SWRST Call function is defined as the following:

1. A Start command is sent by the I²C bus master.
2. The reserved SWRST I²C bus address 1001 011 with the R/W bit set to 0 (write) is sent by the I²C bus master.
3. The TLC59108 device(s) acknowledge(s) after seeing the SWRST Call address 1001 0110 (96h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I²C bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends two bytes with two specific values (SWRST data byte 1 and byte 2):
   1. Byte1 = A5h: the TLC59108 acknowledges this value only. If byte 1 is not equal to A5h, the TLC59108 does not acknowledge it.
   2. Byte 2 = 5Ah: the TLC59108 acknowledges this value only. If byte 2 is not equal to 5Ah, the TLC59108 does not acknowledge it.

If more than two bytes of data are sent, the TLC59108 does not acknowledge any more.

5. Once the correct two bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly acknowledged, the master sends a Stop command to end the SWRST Call. The TLC59108 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (t_BUF).

The I²C bus master may interpret a non-acknowledge from the TLC59108 (at any time) as a SWRST Call Abort. The TLC59108 does not initiate a reset of its registers. This happens only when the format of the Start Call sequence is not correct.

9.3.6 Individual Brightness Control With Group Dimming/Blinking

A 97-kHz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control the individual brightness for each LED.

On top of this signal, one of the following signals can be superimposed (this signal can be applied to the four LED outputs):

• A lower 190-Hz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) provides a global brightness control.
• A programmable frequency signal from 24 Hz to 1/10.73 s (8 bits, 256 steps) provides a global blinking control.

NOTE:

Minimum pulse width for LEDn brightness control is 40 ns.
Minimum pulse width for group dimming is 20.48 μs.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal has two pulses of the LED Brightness Control signal (pulse width = n × 40 ns, with n defined in the PWMx register).
This resulting Brightness + Group Dimming signal shows a resulting control signal with n = 4 (8 pulses).

Figure 7. Brightness and Group Dimming Signals

9.5.1 Characteristics of the I²C Bus

The I²C bus is for two-way two-line communication between different devices or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

9.5.1.1 Bit Transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse as changes in the data line at this time are interpreted as control signals (see Figure 8).

Figure 8. Bit Transfer

9.5.1.2 Start and Stop Conditions

Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is defined as the Stop condition (P) (see Figure 9).

Figure 9. Start and Stop Conditions

9.5.2 System Configuration

A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 10).

Figure 10. System Configuration

9.5.3 Acknowledge

The number of data bytes transferred between the Start and the Stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable the master to generate a Stop condition.

Figure 11. Acknowledge/Not Acknowledge on I²C Bus

Figure 12. Write to a Specific Register

A. See Table 4 for register definitions.

Figure 13. Write to All Registers Using Auto-Increment

Figure 14. Multiple Writes to Individual Brightness Registers Using Auto-Increment

Figure 15. Read All Registers Auto-Increment

A. In this example, several TLC59108 devices are used, and the same Sequence A is sent to each of them.

B. The ALLCALL bit in the MODE1 register is equal to 1 for this example.

C. The OCH bit in the MODE2 register is equal to 1 for this example.

Figure 16. LED All Call I²C Bus Address Programming and LED All Call Sequence

9.5.4 Device Address

Following a Start condition, the bus master must output the address of the slave it is accessing.

9.5.5 Regular I²C Bus Slave Address

The I²C bus slave address of the TLC59108 is shown in Figure 17. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. For buffer management purpose, a set of sector information data should be stored.

Figure 17. Slave Address

The last bit of the address byte defines the operation to be performed. When set to logic 1, a read operation is selected. When set to logic 0, a write operation is selected.

9.5.6 LED All Call I²C Bus Address

• Default power-up value (ALLCALLADR register): 90h or 1001 000
• Programmable through I²C bus (volatile programming)
• At power-up, LED All Call I²C bus address is enabled. TLC59108 sends an ACK when 90h (R/W = 0) or 91h (R/W = 1) is sent by the master.

See LED All Call I2C Bus Address Register (ALLCALLADR) for more detail.

9.5.7 LED Sub Call I²C Bus Address

• Three different I²C bus address can be used
• Default power-up values:
  • SUBADR1 register: 92h or 1001 001
  • SUBADR2 register: 94h or 1001 010
  • SUBADR3 register: 98h or 1001 100
• Programmable through I²C bus (volatile programming)
• At power-up, Sub Call I²C bus address is disabled. TLC59108 does not send an ACK when 92h (R/W = 0) or 93h (R/W = 1) or 94h (R/W = 0) or 95h (R/W = 1) or 98h (R/W = 0) or 99h (R/W = 1) is sent by the master.

See I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3) for more detail.

9.5.8 Software Reset I²C Bus Address

The address shown in Figure 18 is used when a reset of the TLC59108 needs to be performed by the master. The software reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the TLC59108 does not acknowledge the SWRST. See Software Reset for more detail.

Figure 18. Software Reset Address

9.5.9 Control Register

Following the successful acknowledgment of the slave address, LED All Call address or LED Sub Call address, the bus master sends a byte to the TLC59108, which is stored in the Control register. The lowest 5 bits are used as a pointer to determine which register is accessed (D[4:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options (AI[2:0]).

Figure 19. Control Register

When the Auto-Increment flag is set (AI2 = logic 1), the five low order bits of the Control register are automatically incremented after a read or write. This allows the user to program the registers sequentially. Four different types of Auto-Increment are possible, depending on AI1 and AI0 values.

AI[2:0] = 000 is used when the same register must be accessed several times during a single I²C bus communication, for example, changes the brightness of a single LED. Data is overwritten each time the register is accessed during a write operation.

AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.

AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the same I²C bus communication, for example, changing color setting to another color setting.

AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same I²C bus communication, for example, global brightness or blinking change.

AI[2:0] = 111 is used when individually and global changes must be performed during the same I²C bus communication, for example, changing color and global brightness at the same time.

Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits.

When the Control register is written, the register entry point determined by D[4:0] is the first register that is addressed (read or write operation), and can be anywhere between 0 0000 and 1 0001 (as defined in Table 4). When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register increment stops and goes to the next one is determined by AI[2:0]. See Table 3 for rollover values. For example, if the Control register = 1110 1100 (ECh), then the register addressing sequence is (in hex):

0C → ... → 11 → 00 → ... → 0B → 02 → ... → 0B → 02 → ... as long as the master keeps sending or reading data.

9.6.1 Register Descriptions

Table 4 describes the registers in the TLC59108.

9.6.1.9 Output Gain Control Register (IREF)

Table 13 describes the Output Gain Control Register.

Table 13. IREF – Output Gain Control Register (Address 12h) Bit Description

ADDRESS	REGISTER	BIT	SYMBOL	ACCESS (1)	VALUE	DESCRIPTION
12h	IREF	7	CM	R/W	1 (1)	High/low current multiplier
		6	HC	R/W	1 (1)	Subcurrent
		5:0	CC[5:0]	R/W	11 1111 (1)	Current multiplier

I_REF determines the voltage gain (VG), which affects the voltage at the R_EXT terminal and indirectly the reference current (I_REF) flowing through the external resistor at terminal R_EXT. Bit 0 is the Current Multiplier (CM) bit, which determines the ratio I_OUT,target/I_ref. Each combination of VG and CM sets a Current Gain (CG).

• VG: the relationship between {HC,CC[0:5]} and the voltage gain is calculated as shown below:

VG = (1 + HC) × (1 + D/64) / 4

D = CC0 × 2⁵ + CC1 × 2⁴ + CC2 × 2³ + CC3 × 2² + CC4 × 2¹ + CC5 × 2⁰

Where HC is 1 or 0, and D is the binary value of CC[0:5]. So, the VG could be regarded as a floating-point number with 1-bit exponent HC and 6-bit mantissa CC[0:5]. {HC,CC[0:5]} divides the programmable voltage gain VG into 128 steps and two sub-bands:

Low voltage sub-band (HC = 0): VG = 1/4 to 127/256, linearly divided into 64 steps

High voltage sub-band (HC = 1): VG = 1/2 to 127/128, linearly divided into 64 steps

• CM: In addition to determining the ratio I_OUT,target/I_ref, CM limits the output current range.

High Current Multiplier (CM = 1): I_OUT,target/I_ref = 15, suitable for output current range I_OUT = 10 mA to 120 mA.

Low Current Multiplier (CM = 0): I_OUT,target/I_ref = 5, suitable for output current range I_OUT = 5 mA to 40 mA

• CG: The total Current Gain is defined as the following.

V_REXT = 1.26 V × VG

I_ref = V_REXT/R_ext, if the external resistor, R_ext, is connected to ground.

I_OUT,target = I_ref × 15 × 3^{CM – 1} = 1.26 V/R_ext × VG × 15 × 3^CM – 1 = (1.26 V/R_ext × 15) × CG

CG = VG × 3^CM – 1

Therefore, CG = (1/12) to (127/128), and it is divided into 256 steps. If CG = 127/128 = 0.992, the I_OUT,target-R_ext.

Examples

• I_REF Code {CM, HC, CC[0:5]} = {1,1,111111}

VG = 127/128 = 0.992 and CG = VG × 3⁰ = VG = 0.992

• I_REF Code {CM, HC, CC[0:5]} = {1,1,000000}

VG = (1 + 1) × (1 + 0/64)/4 = 1/2 = 0.5, and CG = 0.5

• I_REF Code {CM, HC, CC[0:5]} = {0,0,000000}

VG = (1 + 0) × (1 + 0/64)/4 = 1/4, and CG = (1/4) × 3^–1 = 1/12

After power on, the default value of the Configuration Code {CM, HC, CC[0:5]} is {1,1,111111}. Therefore, VG = CG = 0.992. The relationship between the Configuration Code and the Current Gain is shown in Figure 20.

Figure 20. Current Gain vs Configuration Code