8.3.1.1 Key Event Table

The TCA8418E can be configured to support many different configurations of keypad setups. All 18 GPIOs for the rows and columns can be used to support up to 80 keys in a key pad array. Another option is that all 18 GPIOs be used for GPIs to read 18 buttons which are not connected in an array. Any combination in between is also acceptable (for example, a 3 x 4 keypad matrix and using the remaining 11 GPIOs as a combination of inputs and outputs).

For both types of inputs (keypad matrix and a GPI), a key event can be added to the key event FIFO. The values that are added to the FIFO depend on the configuration (keypad array or GPI) and on which port the press was read on. The tables below show the values that correspond to both types of configurations.

Key values below are represented in decimal values, because the 10s place is used to mark the row, and the ones place is used to denote the column. It is more clear to see the numbering convention used when viewed in decimal values.

8.3.1.2 General Purpose Input (GPI) Events

A column or row configured as GPI can be programmed to be part of the Key Event Table, hence becomes also capable of generating Key Event Interrupt. A Key Event Interrupt caused by a GPI follow the same process flow as a Key Event Interrupt caused by a Key press.

GPIs configured as part of the Key Event Table allows for single key switches to be monitored as well as other GPI interrupts. As part of the Event Table, GPIs are represented with decimal value of 97 and run through decimal value of 114. R0-R7 are represented by 97-104 and C0-C9 are represented by 105-114

For a GPI that is set as active high, and is enabled in the Key Event Table, the state-machine will add an event to the event count and event table whenever that GPI goes high. If the GPI is set to active low, a transition from high to low will be considered a press and will also be added to the event count and event table. Once the interrupt state has been met, the state machine will internally set an interrupt for the opposite state programmed in the register to avoid polling for the released state, hence saving current. Once the released state is achieved, it will add it to the event table. The press and release will still be indicated by bit 7 in the event register.

The GPI Events can also be used as unlocked sequences. When the GPI_EM bit is set, GPI events will not be tracked when the keypad is locked. GPI_EM bit must be cleared for the GPI events to be tracked in the event counter and table when the keypad is locked.

8.3.1.3 Key Event (FIFO) Reading

The TCA8418E has a 10-byte event FIFO, which stores any key presses or releases which have been configured to be added to the Key Event Table. All ROWs and COLs added to the keypad matrix via the KP_GPIO1-3 Registers will have any key pad events added to the FIFO. Any GPIs configured with a 1 in the GPI_EM1-3 Registers will also be part of the event FIFO.

When the host wishes to read the FIFO, the following procedure is recommended.

1. Read the INT_STAT (0x02) register to determine what asserted the INT line. If GPI_INT or K_INT is set, then a key event has occurred, and the event is stored in the FIFO.
2. Read the KEY_LCK_EC (0x03) register, bits [3:0] to see how many events are stored in FIFO.
3. Read the KEY_EVENT_A (0x04) register. Bit 7 value '0' signifies key release, value 1 signifies key press. Bits [6:0] state which key was pressed with respect to the Key Event Table. With each read of the key event register, the event counter in KEY_LCK_EC[3:0] will decrease by 1, and the FIFO will shift the events down 1 register.
4. Repeat step 3 until either KEY_LCK_EC[3:0] = 0 or KEY_EVENT_A = 0. This signifies that the FIFO is empty.
5. Reset the INT_STAT interrupt flag which was causing the interrupt by writing a 1 to the specific bit.

As an example, consider the following key presses.

If this example key sequence occurs, then while performing the recommended read procedure listed above, the host would see the following information. Information at the top of the list is of an initial read to the KEY_LCK_EC[3:0] register.

8.3.1.4 Key Event Overflow

The TCA8418E has the ability to handle an overflow of the key event FIFO. An overflow event occurs when the FIFO is full of events (10 key events are stored) and a new key event occurs. In short, this means that the TCA8418E does not have the ability to hold any more key press information in the internal buffer. When this occurs, the OVR_FLOW_INT bit in the INT_STAT Register is set, and if the OVR_FLOW_IEN bit is set in the CFG Register, then the INT output will be asserted low to let the processor know that an overflow has occurred.

The TCA8418E has the ability to handle an overflow in 1 of two ways, which is determined by the bit value of the OVR_FLOW_M bit in the CFG Register.

Consider the example below, if the FIFO is full of the key presses and a new key press comes in. This new overflow key press will be a key press of key 2 (0x82 is the hex representation of a key 2 press event)

8.3.5.1 50-µs Interrupt Configuration

8.4.2.1 Idle Key Scan Mode

Once the TCA8418E has had the keypad array configured, it will enter idle mode when no keys are being pressed. All columns configured as part of the keypad array will be driven low and all rows configured as part of the keypad array will be set to inputs, with pullup resistors enabled. During idle mode, the internal oscillator is turned off so that power consumption is low as the device awaits a key press.

8.4.2.2 Active Key Scan Mode

When the TCA8418E is in idle key scan mode, the device awaits a key press. Once a key is pressed in the array, a low signal on one of the ROW pin inputs triggers an interrupt, which will turn on the internal oscillator and enter the active key scan mode. At this point, the TCA8418E will start the key scan algorithm to determine which key is being pressed, and/or it will use the internal oscillator for debouncing. Once all keys have been released, the device will enter idle key scan mode.

8.5.2.1 Writes

To write on the I²C bus, the master will send a START condition on the bus with the address of the slave, as well as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master will then send the register address of the register to which it wishes to write. The slave will acknowledge again, letting the master know it is ready. After this, the master will start sending the register data to the slave until the master has sent all the data necessary (which is sometimes only a single byte), and the master will terminate the transmission with a STOP condition.

Figure 24 shows an example of writing a single byte to a register.

Figure 24. Write to Register

Figure 25. Write to Configuration Register

8.5.2.2 Reads

Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave, the master must first instruct the slave which register it wishes to read from. This is done by the master starting off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0 (signifying a write), followed by the register address it wishes to read from. Once the slave acknowledges this register address, the master will send a START condition again, followed by the slave address with the R/W bit set to 1 (signifying a read). This time, the slave will acknowledge the read request, and the master will release the SDA bus but will continue supplying the clock to the slave. During this part of the transaction, the master will become the master-receiver, and the slave will become the slave-transmitter.

The master will continue to send out the clock pulses, but will release the SDA line so that the slave can transmit data. At the end of every byte of data, the master will send an ACK to the slave, letting the slave know that it is ready for more data. Once the master has received the number of bytes it is expecting, it will send a NACK, signaling to the slave to halt communications and release the bus. The master will follow this up with a STOP condition.

Figure 26 shows an example of reading a single byte from a slave register.

Figure 26. Read from Register

Table 8. TCA8418E Device Addresses

Table 9. Register Descriptions

8.6.2.1 Configuration Register (Address 0x01)

Bit 7 in this register is used to determine the programming mode. If it is low, all data bytes are written to the register defined by the command byte. If bit 7 is high, the value of the command byte is automatically incremented after each byte is written, and the next data byte is stored in the corresponding register. Registers are written in the sequence shown in Table 9. Once the GPIO_PULL3 register (0x2E) is written to, the command byte returns to register 0. Registers 0 and 2F are reserved and a command byte that references these registers is not acknowledged by the TCA8418E.

The keypad lock interrupt enable determines if the interrupt pin is asserted when the key lock interrupt (see Interrupt Status Register) bit is set.

8.6.2.2 Interrupt Status Register, INT_STAT (Address 0x02)

The INT_STAT register is used to check which type of interrupt has been triggered. If the corresponding interrupt enable bits are set in the Configuration Register, then a value of 1 in the corresponding bit will assert the INT line low. An exception to this is the CAD_INT bit, which will assert the CAD_INT pin on YFP packages.

A read to this register will return which types of events have occurred. Writing a 1 to the bit will clear the interrupt, unless there is still data which has set the Interrupt (unread keys in the FIFO).

8.6.2.3 Key Lock and Event Counter Register, KEY_LCK_EC (Address 0x03)

KEC[3:0] indicates how many key events are in the FIFO. For example, KEC[3:0] = 0b0000 = 0 events, KEC[3:0] = 0b0001 = 1 event and KEC[3:0] = 0b1010 = 10 events. As events happen (press or release), the count increases accordingly.

8.6.2.4 Key Event Registers (FIFO), KEY_EVENT_A–J (Address 0x04–0x0D)

These registers – KEY_EVENT_A-J – function as a FIFO stack which can store up to 10 key presses and releases. The user first checks the INT_STAT register to see if there are any interrupts. If so, then the Key Lock and Event Counter Register (KEY_LCK_EC, register 0x03) is read to see how many interrupts are stored. The INT_STAT register is then read again to ensure no new events have come in. The KEY_EVENT_A register is then read as many times as there are interrupts. Each time a read happens, the count in the KEY_LCK_EC register reduces by 1. The data in the FIFO also moves down the stack by 1 too (from KEY_EVENT_J to KEY_EVENT_A). Once all events have been read, the key event count is at 0 and then KE_INT bit can be cleared by writing a ‘1’ to it.

In the KEY_EVENT_A register, KEA[6:0] indicates the key # pressed or released. A value of 0 to 80 indicate which key has been pressed or released in a keypad matrix. Values of 97 to 114 are for GPI events.

Bit 7 or KEA[7] indicate if a key press or key release has happened. A ‘0’ means a key release happened. A ‘1’ means a key has been pressed (which can be cleared on a read).

For example, 3 key presses and 3 key releases are stored as 6 words in the FIFO. As each word is read, the user knows if it is a key press or key release that occurred. Key presses such as CTRL+ALT+DEL are stored as 3 simultaneous key presses. Key presses and releases generate key event interrupts. The KE_INT bit and /INT pin will not cleared until the FIFO is cleared of all events.

All registers can be read but for the purpose of the FIFO, the user should only read KEY_EVENT_A register. Once all the events in the FIFO have been read, reading of KEY_EVENT_A register will yield a zero value.

8.6.2.5 Keypad Lock1 to Lock2 Timer Register, KP_LCK_TIMER (Address 0x0E)

KL[2:0] are for the Lock1 to Lock2 timer

KL[7:3] are for the interrupt mask timer

Lock1 to Lock2 timer must be non-zero for keylock to be enabled. The lock1 to lock2 bits ( KL[2:0] ) define the time in seconds the user has to press unlock key 2 after unlock key 1 before the key lock sequence times out. For more information, please see Keypad Lock/Unlock.

If the keypad lock interrupt mask timer is non-zero, a key event interrupt (K_INT) will be generated on any first key press. The second interrupt (K_LCK_IN) will only be generated when the correct unlock sequence has been completed. If either timer expires, the keylock state machine will reset.

When the interrupt mask timer is disabled (‘0’), a key lock interrupt will trigger only when the correct unlock sequence is completed.

The interrupt mask timer should be set for the time it takes for the LCD to dim or turn off. For more information, please see Keypad Lock Interrupt Mask Timer.

8.6.2.6 Unlock1 and Unlock2 Registers, UNLOCK1/2 (Address 0x0F-0x10)

UK1[6:0] contains the key number used to unlock key 1

UK2[6:0] contains the key number used to unlock key 2

A ‘0’ in either register will disable the keylock function.

8.6.2.7 GPIO Interrupt Status Registers, GPIO_INT_STAT1–3 (Address 0x11–0x13)

These registers are used to check GPIO interrupt status. If the GPI_INT bit is set in INT_STAT register, then the GPI which set that interrupt will be marked with a 1 in the corresponding table. To clear the GPI_INT bit, these registers must all be 0x00. A read to the register will clear it.

8.6.2.8 GPIO Data Status Registers, GPIO_DAT_STAT1–3 (Address 0x14–0x16)

These registers show the GPIO state when read for inputs and outputs. Read these twice to clear them.

8.6.2.9 GPIO Data Out Registers, GPIO_DAT_OUT1–3 (Address 0x17–0x19)

These registers contain GPIO data to be written to GPIO out driver; inputs are not affected. This sets the output for the corresponding GPIO output.

8.6.2.10 GPIO Interrupt Enable Registers, GPIO_INT_EN1–3 (Address 0x1A–0x1C)

These registers enable interrupts (bit value 1) or disable interrupts (bit value '0') for general purpose inputs (GPI) only. If the input changes on a pin which is setup as a GPI, then the GPI_INT bit will be set in the INT_STAT register.

A bit value of '0' in any of the unreserved bits disables the corresponding pin's ability to generate an interrupt when the state of the input changes. This is the default value.

A bit value of 1 in any of the unreserved bits enables the corresponding pin's ability to generate an interrupt when the state of the input changes.

8.6.2.11 Keypad or GPIO Selection Registers, KP_GPIO1–3 (Address 0x1D–0x1F)

A bit value of '0' in any of the unreserved bits puts the corresponding pin in GPIO mode. A pin in GPIO mode can be configured as an input or an output in the GPIO_DIR1-3 registers. This is the default value.

A 1 in any of these bits puts the pin in key scan mode and becomes part of the keypad array, then it is configured as a row or column accordingly (this is not adjustable).

8.6.2.12 GPI Event Mode Registers, GPI_EM1–3 (Address 0x20–0x22)

A bit value of '0' in any of the unreserved bits indicates that it is not part of the event FIFO. This is the default value.

A 1 in any of these bits means it is part of the event FIFO. When a pin is setup as a GPI and has a value of 1 in the Event Mode register, then any key presses will be added to the FIFO. Please see Key Event Table for more information.

8.6.2.13 GPIO Data Direction Registers, GPIO_DIR1–3 (Address 0x23–0x25)

A bit value of '0' in any of the unreserved bits sets the corresponding pin as an input. This is the default value.

A 1 in any of these bits sets the pin as an output.

8.6.2.14 GPIO Edge/Level Detect Registers, GPIO_INT_LVL1–3 (Address 0x26–0x28)

A bit value of '0' indicates that interrupt will be triggered on a high-to-low/low-level transition for the inputs in GPIO mode. This is the default value.

A bit value of 1 indicates that interrupt will be triggered on a low-to-high/high-level value for the inputs in GPIO mode.

8.6.2.15 Debounce Disable Registers, DEBOUNCE_DIS1–3 (Address 0x29–0x2B)

This is for pins configured as inputs. A bit value of ‘0’ in any of the unreserved bits enables the debounce. This is the default value

A bit value of ‘1’ disables the debounce.

Figure 27. Debounce Enabled and Disabled

Debounce disable will have the same effect for GPI mode or for rows in keypad scanning mode. The RESET input always has a 50-μs debounce time.

The debounce time for inputs is the time required for the input to be stable to be noticed. This time is 50 μs.

The debounce time for the keypad is for the columns only. The minimum time is 25 ms. All columns are scanned once every 25 ms to detect any key presses. Two full scans are required to see if any keys were pressed. If the first scan is done just after a key press, it will take 25 ms to detect the key press. If the first scan is down much later than the key press, it will take 40 ms to detect a key press.

8.6.2.16 GPIO Pullup Disable Register, GPIO_PULL1–3 (Address 0x2C–0x2E)

This register enables or disables pullup registers from inputs.

A bit value of '0' will enable the internal pullup resistors. This is the default value.

A bit value of 1 will disable the internal pullup resistors.