9.3.1 Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the Dual Mode^[1] DisplayPort inputs and outputs are high impedance. It is critical to transition the OE input from a low level to a high level after the V_CC supply has reached the minimum recommended operating voltage. Achieve this transition by a control signal to the OE input, or by an external capacitor connected between OE and GND. To ensure that the SNx5DP149 device is properly reset, the OE pin must be de-asserted for at least 100-μs before being asserted. When OE is toggled in this manner the device is reset. This requires the device to be reprogrammed if it was originally programmed through I²C for configuration. When implementing the external capacitor, the size of the external capacitor depends on the power-up ramp of the V_CC supply, where a slower ramp-up results in a larger value external capacitor. Refer to the latest reference schematic for SNx5DP149; consider approximately 200-nF capacitor as a reasonable first estimate for the size of the external capacitor. Both OE implementations are shown in Figure 19 and Figure 20.

SPACE

Figure 19. External Capacitor Controlled OE

Figure 20. OE Input from Active Controller

9.3.2 Operation Timing

SNx5DP149 starts to operate after the OE signal goes high (see Figure 21, Figure 22, and Table 1). Keeping OE low until V_DD and V_CC become stable avoids any timing requirements as shown in Figure 21.

Figure 21. Power-Up Timing for SNx5DP149

Figure 22. CDR Timing for SNx5DP149

9.3.3 Input Lane Swap and Polarity Working

The SNx5DP149 device incorporates the swap function, which can set the input lanes in swap mode. The IN_D2 routes to the OUT_CLK position. The IN_D1 swaps with IN_D0. The swap function only changes the input pins; EQ setup follows new mapping. The user needs to control the register 0x09h bit 7 for SWAP enable. Lane swap is operational in both redriver and retimer mode.

Figure 23. SNx5DP149 Swap Function for 40 Pins

The SNx5DP149 can also change the polarity of the input signals. Use Register 0x9h bit 6 to swap polarity using I²C. Polarity swap only works for retimer mode. When the device is in automatic redriver to retimer mode this only works when device is in retimer stage. If set and data rate falls below 1.0-Gbps in this mode the polarity function will be lost.

9.3.4 Main Link Inputs

Standard Dual Mode^[1] DisplayPort terminations are integrated on all inputs with expected AC coupling capacitors on board prior to input pins. External terminations are not required. Each input data channel contains an adaptive or fixed equalizer to compensate for cable or board losses. The voltage at the input pins must be limited below the absolute maximum ratings. The input pins have incorporated failsafe circuits. The input pins can be polarity changed through the local I2C register.

9.3.5 Main Link Inputs Debug Tools

There are two methods for debugging a system making sure the inputs to the SNx5DP149 are valid. A TMDS error checker is implemented that will increment an error counter per data lane. This allows the system implementer to determine how the link between the source and SNx5DP149 is performing on all three data lanes. See CSR Bit Field Definitions – RX PATTERN VERIFIER CONTROL/STATUS register in Table 10.

If a high error count is evident, the SNx5DP149 has the ability to provide the general eye quality. A tool is available that uses the I²C^[4] link to download data that can be plotted for an eye diagram. This is available per data lane.

9.3.6 Receiver Equalizer

Equalizers are used to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. The SNx5DP149 device supports both fixed receiver equalizer (redriver and retimer mode) and adaptive receive equalizer (retimer mode) by setting the EQ_SEL/A0 pin or through I²C using reg0Ah[5]. When the EQ_SEL/A0 pin is high, the EQ gain is fixed to 14-dB. The EQ gain will be 7.5-dB if the EQ_SEL/A0 pin is set low. The SNx5DP149 device operates in adaptive equalizer mode when EQ_SEL/A0 left floating. Using adaptive equalization the gain will be automatically adjusted based on the data rate to compensate for variable trace or cable loss. Using the local I²C^[4] control, reg0Dh[5:1], the fixed EQ gain can be selected for both data and clock.

Figure 24. Adaptive EQ Gain Curve

9.3.7 Termination Impedance Control

For HDMI1.4b^[2] when data rate over 2 Gbps, the output performance could be better if the termination value between 150 to 300-Ω which was allowed. For compliance this may not be the best solution so be prepared to utilize no termination. The SNx5DP149 supports two different source termination impedances for HDMI1.4b^[2] . This can be adjusted by I²C^[4]; reg0Bh[4:3] TX_TERM_CTL.

9.3.8 TMDS Outputs

An 1% precision resistor, 6.5-kΩ, is recommended to be connected from Vsadj pin to ground to allow the differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10-mA current sink capability when no source term is enabled, which provides a typical 500-mV voltage drop across a 50-Ω termination resistor. As compliance testing is system dependant this resistor value can be adjusted.

Figure 25. TMDS Driver and Termination Circuit

Referring to Figure 25, if both V_CC (device supply) and AVCC (sink termination supply) are powered, the TMDS output signals are high impedance when OE = low. The normal operating condition is that both supplies are active. A total of 33-mW of power is consumed by the terminations independent of the OE logical selection. When AVCC is powered on, normal operation (OE controls output impedance) is resumed. When the power source of the device is off and the power source to termination is on, the IO(off) (output leakage current) specification ensures the leakage current is limited 45-μA or less.

The clock and data lanes V_OD can be changed through I²C^[4] (see VSWING_CLK and VSWING_DATA in Table 8 for details). shows the different output voltage based on different Vsadj resistor values.

9.3.8.1 Pre-Emphasis/De-Emphasis

The SNx5DP149 provides De-emphasis as a way to compensate for the ISI loss between the TMDS outputs and the receiver it is driving. There are two methods to implement this function. When in pin strapping mode the PRE_SEL pin controls this. The PRE_SEL pin provides –2-dB, or 0-dB de-emphasis, which allows output signal pre-conditioning to offset interconnect losses from the SNx5DP149 device outputs to a TMDS receiver. TI recommends setting PRE_SEL at 0 dB while connecting to a receiver through a short PCB route. When pulled to ground with a 65-kΩ resistor –2-dB can be realized, see Figure 9. When using I²C, Reg0Ch[1:0] is used to make these adjustments.

As there are times true pre-emphasis may be the best solution there are two ways to accomplish this. If pin strapping is being use the best method is to reduce the Vsadj resistor value increasing the V_OD and then pulling the PRE_SEL pin to ground using the 65-kΩ resistor, see Figure 26. If using I²C this can be accomplished using two methods. First is similar to pin strapping by adjusting the Vsadj resistor value and then implementing –2-dB de-emphasis. Second method is to set Reg0Ch[7:5] = 011 and the set Reg0Ch[1:0] = 01 which accomplishes the same pre-emphasis setting. See Figure 27.

Figure 26. Pre-Emphasis Using Pin Strapping Method

Figure 27. Pre-Emphasis Using I²C Method

9.4.1 Retimer Mode

Clock and data recovery circuits (CDR) are used to track, sample and retime the equalized data bit streams. The CDRs are designed with loop bandwidth to minimize the amount of jitter transfer from the video source to the TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1-MHz, will be transferred to the TMDS outputs. Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce the amount of high frequency jitter from the video source. The retimer is automatically activated at pixel clock above approximately 100-MHz when jitter cleaning is needed for robust operation. The retimer operates at about 1.0 to 3.4-Gbps DR supporting HDMI1.4b^[3]. At pixel clock frequency below about 100 MHz, the SNx5DP149 automatically bypasses the internal retimer and operates as a redriver. When the video source changes resolution, the internal retimer starts the acquisition process to determine the input clock frequency and acquire lock to the new data bit streams. During the clock frequency detection period and the retimer acquisition period (that last approximately 7-ms), the TMDS drivers can be kept active (default) or programmed to be disabled to avoid sending invalid clock or data to the downstream receiver.

9.4.2 Redriver Mode

The SNx5DP149 also has a redriver mode that can be enabled through I²C^[4]; at offset address 0Ah bits 1:0 DEV_FUNC_MODE. When in this mode, the CDR and PLL are shut off, thus reducing power. Jitter performance is degraded as the device will now only compensate for ISI loss in the link. In redriver mode HDMI1.4b^[3] compliance is not guaranteed as skew compensation and retiming functions are disabled. Excessive random or phase jitter will not be compensated.

9.4.3 DDC Functional Description

The SNx5DP149 solves sink- or source-level issues by implementing a master/slave control mode for the DDC bus. When the SNx5DP149 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it will transfer the data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the feedback from the downstream device, the SNx5DP149 will pull up or pull down the SDA_SRC bus and deliver the signal to the source.

The DDC link defaults to 100 kbps, but can be set to various values including 400 kbps by setting the correct value to address 22h (see Table 3) through the I²C access on the DDC interface. The DDC lines are 5-V tolerant. The HPD_SRC goes to high impedance when VCC is under low power conditions, < 1.5-V.

9.5.1 DP-HDMI Adaptor ID Buffer

The SNx5DP149 device includes the DP-HDMI adapter ID buffer for HDMI/DVI adaptor recognition, defined by the VESA DisplayPort Dual-Mode Standard Version 1.1, accessible by standard I²C^[4] protocols through the DDC interface when the HDMI_SEL/A1 pin is low. The DP-HDMI adapter buffer and extended DDC register for Type 2 capability is accessed at target addresses 80h (Write) and 81h (Read).

The DP-HDMI adapter buffer contains a read-only phrase DP-HDMI ADAPTOR<EOT> converted to ASCII characters, as shown in Table 3, and supports the WRITE command procedures (accessed at target address 80h) to select the subaddress, as recommended in the VESA DisplayPort Interoperability Guideline Adaptor Checklist Version 1.0 section 2.3.

9.5.2 Local I²C Interface Overview

The SCL_CTL and SDA_CTL pins are used for I²C clock and I²C data respectively. The SNx5DP149 I²C interface conforms to the 2-wire serial interface defined by the I²C Bus Specification, Version 2.1 (January 2000), and supports the fast mode transfer up to 400 kbps.

The device address byte is the first byte received following the start condition from the master device. The 7-bit device address for the SNx5DP149 device decides by the combination of EQ_SEL/A0 and HDMI_SEL/A1. Table 4 clarifies the SNx5DP149 device target address.

9.5.3 I²C Control Behavior

Follow this procedure to write to the SNx5DP149 device I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the SNx5DP149 device 7-bit address and a zero-value W/R bit to indicate a write cycle.
2. The SNx5DP149 device acknowledges the address cycle by combination of A0 and A1.
3. The master presents the subaddress (I²C register within SNx5DP149 device) to be written, consisting of one byte of data, MSB-first.
4. The SNx5DP149 device acknowledges the subaddress cycle.
5. The master presents the first byte of data to be written to the I²C register.
6. The SNx5DP149 device acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the SNx5DP149.
8. The master terminates the write operation by generating a stop condition (P).

Follow this procedure to read the SNx5DP149 I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the SNx5DP149 7-bit address and a zero-value W/R bit to indicate a write cycle.
2. The SNx5DP149 device acknowledges the address cycle by combination of A0 and A1.
3. The master presents the subaddress (I2C register within SNx5DP159 device) to be read, consisting of one byte of data, MSB-first.
4. The SNx5DP149 device acknowledges the subaddress cycle.
5. The master initiates a read operation by generating a start condition (S), followed by the SNx5DP149 7-bit address and a one-value W/R bit to indicate a read cycle.
6. The SNx5DP159 device acknowledges the address cycle.
7. The SNx5DP149 device transmit the contents of the memory registers MSB-first starting at the written subaddress.
8. The SNx5DP149 device will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I²C master acknowledges reception of each data byte transfer.
9. If an ACK is received, the SNx5DP149 device transmits the next byte of data.
10. The master terminates the read operation by generating a stop condition (P).

Refer to Table 6 for the SNx5DP149 device local I²C register descriptions. Reads from reserved fields return 0s and writes are ignored.

9.5.4 I²C Control and Status Registers

Reads from reserved fields return 0, and writes to read-only reserved registers are ignored. Writes to reserved registers, which are marked with ‘W’, produce unexpected behavior. All addresses not defined by this specification are considered reserved. Reads from these addresses return 0 and writes will be ignored.