Table 1. 4–Level Control Pin Settings

8.3.1 Typical 4-Level Input Thresholds

• Internal Threshold between 0 and R = 0.2 * V_IN or V_DD
• Internal Threshold between R and F = 0.5 * V_IN or V_DD
• Internal Threshold between F and 1 = 0.8 * V_IN or V_DD

In order to minimize the startup current associated with the integrated 2.5 V regulator, the 1 kΩ pull-up / pull-down resistors are recommended. If several four level inputs require the same setting, it is possible to combine two or more 1 kΩ resistors into a single lower value resistor. As an example, combining two inputs with a single 500 Ω resistor is a valid way to save board space.

8.4.1 Pin Control Mode

When in Pin Mode (ENSMB = 0), equalization, de-emphasis, and VOD (output amplitude) can be selected via external pin control for both the A-channel and B-channel. Equalization and de-emphasis can be programmed by pin selection for each side independently. For further device control, the VOD_SEL and MODE pins are available to improve DS100BR111A performance depending on design applications. The receiver electrical idle detect threshold is also adjustable via the SD_TH pin. Pin control mode is ideal in situations where neither MCU or EEPROM is available to access the device via SMBus SDA and SCL lines.

8.4.2 SMBus Slave Mode

When in Slave SMBus Mode (ENSMB = 1), equalization, de-emphasis, and VOD (output amplitude) are all programmable on an individual channel basis. Upon assertion of ENSMB, the EQx, DEMx, and VODx settings are controlled by SMBus immediately. It is important to note that SMBus settings can only be changed from their defaults after asserting Register Enable by setting Reg 0x06[3] = 1. The EQx, DEMx, and VODx pins are subsequently converted to AD0-AD3 SMBus address inputs. The other external control pins (TX_DIS, MODE, and SD_TH) remain active unless their respective registers are written to and the appropriate override bit is set. If the user overrides a pin control, the input voltage level of that control pin is ignored until ENSMB is driven low (Pin Mode). In the event that channels are powered down via the TX_DIS pin, register setting states are not affected.

Table 2. Signal Detect Threshold Level⁽¹⁾

8.4.3 SMBus Master Mode

When in SMBus Master Mode (ENSMB = Float), the equalization, de-emphasis, and VOD (output amplitude) for multiple devices can be loaded via external EEPROM. By asserting a Float condition on the ENSMB pin, an external EEPROM writes register settings to each device in accordance with its SMBus slave address. The settings programmable by external EEPROM provide only a subset of all the register bits available via SMBus Slave Mode, and the bit-mapping between SMBus Slave Mode registers and EEPROM addresses can be referenced in Table 6. Once the EEPROM successfully finishes loading each device's register settings, the device reverts back to SMBus Slave Mode and releases SDA and SCL control to an external master MCU. If the EEPROM fails to load settings to a particular device, for example due to an invalid or blank hex file, the device waits indefinitely in an unknown state where access to the SMBus lines is not possible.

8.4.4 Signal Conditioning Settings

Equalization, de-emphasis, and VOD settings accessible via the pin controls are chosen to meet the needs of most high speed applications. For additional levels and flexibility in EQ, de-emphasis, and VOD programming, these settings can be controlled via the SMBus registers. Each control pin input has a total of four possible voltage level settings. In pin mode, Table 3 shows the 16 EQ settings available, and Table 4 shows the 16 de-emphasis and VOD combination settings available. Note that when in pin mode, only 16 of a possible 256 EQ programmable levels can be accessed by setting the EQx[1:0] pins. In addition, each pin setting applied to the VOD_SEL and DEMx pin input programs a fixed combination of VOD and de-emphasis. In order to access all 256 EQ levels and control both VOD and de-emphasis settings independently, SMBus register access must be used.

8.5.1 System Management Bus (SMBus) and Configuration Registers

The System Management Bus interface is compatible with the SMBus 2.0 physical layer specification. Tie ENSMB = 1 kΩ to VDD (2.5 V mode) or VIN (3.3 V mode) to enable SMBus Slave Mode and allow access to the configuration registers.

The DS100BR111A uses AD[3:0] inputs in both SMBus Modes. These AD[3:0] pins are the user set SMBus slave address inputs and have internal pull-downs. Based on the SMBus 2.0 specification, the DS100BR111A has a 7-bit slave address. The LSB is set to 0'b (for a WRITE). When AD[3:0] pins are left floating or pulled low, AD[3:0] = 0000'b, and the device default address byte is 0xB0. The device supports up to 16 address bytes, as shown in Table 5.

The SDA and SCL pins are 3.3 V tolerant, but are not 5 V tolerant. An external pull-up resistor is required on the SDA and SCL line. The resistor value can be from 2 kΩ to 5 kΩ depending on the voltage, loading, and speed.

8.5.2 Transfer Of Data Via the SMBus

During normal operation, the data on SDA must be stable during the time when SCL is High.

There are three unique states for the SMBus:

START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.

STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.

IDLE: If SCL and SDA are both High for a time exceeding t_BUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for t_HIGH, then the bus will transfer to the IDLE state.

8.5.3 SMBus Transactions

The device supports WRITE and READ transactions. See Table 9 for register address, type (Read/Write, Read Only), default value, and function information.

8.5.4 Writing a Register

To write a register, the following protocol is used (see SMBus 2.0 specification):

1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.

Once the WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur.

8.5.5 Reading a Register

To read a register, the following protocol is used (see SMBus 2.0 specification):

1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.

Once the READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur.

Please see Table 9 for more information.

8.5.6 EEPROM Programming

The DS100BR111A supports reading directly from an external EEPROM device by implementing SMBus Master mode. When used in SMBus Master mode, the DS100BR111A will read directly from a specific location in the external EEPROM. When designing a system that uses external EEPROM, the following guidelines should be followed:

• Set the DS100BR111A in SMBus Master Mode.
  • ENSMB (Pin 3) = Float
• The external EEPROM device must support 1 MHz operation.
• The external EEPROM device address byte must be 0xA0.
• Set the AD[3:0] inputs for SMBus address byte. When AD[3:0] = 0000'b, the device address byte is 0xB0.
• The device address can be set with the use of the AD[3:0] input up to 16 different addresses. Use the example below to set each of the SMBus addresses.
  • AD[3:0] = 0001'b, the device address byte is 0xB2
  • AD[3:0] = 0010'b, the device address byte is 0xB4
  • AD[3:0] = 0011'b, the device address byte is 0xB6
  • AD[3:0] = 0100'b, the device address byte is 0xB8
• The master implementation in the DS100BR111A supports multiple devices reading from one EEPROM. When tying multiple devices to the SDA and SCL pins, use these guidelines:
  • Use adjacent SMBus addresses for the 4 devices
  • Use a pull-up resistor on SDA; value = 4.7 kΩ
  • Use a pull-up resistor on SCL: value = 4.7 kΩ
  • Daisy-chain READEN (Pin 17) and DONE (Pin 18) from one device to the next device in the sequence.
    1. Tie READEN of the 1st device in the chain (U1) to GND
    2. Tie DONE of U1 to READEN of U2
    3. Tie DONE of U2 to READEN of U3
    4. Tie DONE of U3 to READEN of U4
    5. Optional: Tie DONE of U4 to a LED to show each of the devices have been loaded successfully

8.5.6.1 Master EEPROM Programming

Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS100BR111A device. The first 3 bytes of the EEPROM always contain a header common and necessary to control initialization of all devices connected to the same SMBus line. There is a CRC enable flag to enable or disable CRC checking. There is a MAP bit to flag the presence of an address map that specifies the configuration data start address in the EEPROM. If the MAP bit is not present, the configuration data start address immediately follows the 3-byte base header. A bit to indicate an EEPROM size > 256 bytes is necessary to address the EEPROM properly. There are 37 bytes of data size for each DS100BR111A device. For more details about EEPROM programming and Master mode, refer to SNLA228.

Figure 8. Typical EEPROM Data Set

NOTE

The maximum EEPROM size supported is 8 kbits (1024 x 8 bits).

The CRC-8 calculation is performed for each device on the first 3 bytes of header information plus the 37 bytes of data for the DS100BR111A or 40 bytes in total. The result of this calculation is placed immediately after the DS100BR111A data in the EEPROM which ends with "5454". The CRC-8 in the DS100BR111A uses a polynomial = x⁸ + x² + x + 1.

There are two pins that provide unique functions in SMBus Master mode:

• DONE
• READEN

When the DS100BR111A is powered up in SMBus Master mode, it reads its configuration from the external EEPROM when the READEN pin goes low. When the DS100BR111A is finished reading its configuration from the external EEPROM, it drives the DONE pin low. In applications where there is more than one DS100BR111A on the same SMBus, bus contention can result if more than one DS100BR111A tries to take control of the SMBus at the same time. The READEN and DONE pins prevent this bus contention. The system should be designed so that the READEN pin from one DS100BR111A in the system is driven low on power-up. This DS100BR111A will take command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When the first DS100BR111A is finished reading its configuration, it will drive the DONE pin low. This pin should be connected to the READEN pin of another DS100BR111A. When this second DS100BR111A senses its READEN pin driven low, it will take command of the SMBus and read its initial configuration from the external EEPROM, after which it will set its DONE pin low. By connecting the DONE pin of each DS100BR111A to the READEN pin of the next DS100BR111A, each DS100BR111A can read its initial configuration from the EEPROM without causing bus contention.

Figure 9. Typical Multi-Device EEPROM Connection Diagram

Table 9. SMBus Slave Mode Register Map