ZHCSFZ0D December 2016 – December 2023 DAC38RF80 , DAC38RF83 , DAC38RF84 , DAC38RF85 , DAC38RF90 , DAC38RF93
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | x |
| W0C | W0C | W0C | W0C | W0C | W0C | W0C | W0C |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| W0C | W0C | W0C | W0C | W0C | W0C | W0C | W0C |
| LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | ALM_DIV8_ZERO | W0C | 0 | Asserted if the clkdiv8 in the CDRV_SER shift register is all zeros. |
| 14 | ALM_DIV12_ZERO | W0C | 0 | Asserted if the clkdiv12 in the CDRV_SER shift register is all zeros. |
| 13 | ALM_DIV16_ZERO | W0C | 0 | Asserted if the clkdiv16 in the CDRV_SER shift register is all zeros. |
| 12 | ALM_DIV24_ZERO | W0C | 0 | Asserted if the clkdiv24 in the CDRV_SER shift register is all zeros. (Connected to the div18 port) |
| 11 | ALM_DIV20_ZERO | W0C | 0 | Asserted if the clkdiv20 in the CDRV_SER shift register is all zeros. |
| 10 | ALM_DIV32_ZERO | W0C | 0 | Asserted if the clkdiv32 in the CDRV_SER shift register is all zeros. |
| 9 | ALM_DIV36_ZERO | W0C | 0 | Asserted if the clkdiv36 in the CDRV_SER shift register is all zeros. |
| 8 | ALM_DIV40_ZERO | W0C | 0 | Asserted if the clkdiv40 in the CDRV_SER shift register is all zeros. |
| 7 | ALM_DIV48_ZERO | W0C | 0 | Asserted if the clkdiv48 in the CDRV_SER shift register is all zeros. |
| 6 | ALM_DIV64_ZERO | W0C | 0 | Asserted if the clkdiv64 in the CDRV_SER shift register is all zeros. |
| 5 | ALM_DIV72_ZERO | W0C | 0 | Asserted if the clkdiv72 in the CDRV_SER shift register is all zeros. |
| 4 | ALM_DIV80_ZERO | W0C | 0 | Asserted if the clkdiv80 in the CDRV_SER shift register is all zeros. |
| 3 | ALM_DIV96_ZERO | W0C | 0 | Asserted if the clkdiv96 in the CDRV_SER shift register is all zeros. |
| 2 | ALM_DIV128_ZERO | W0C | 0 | Asserted if the clkdiv128 in the CDRV_SER shift register is all zeros. |
| 1 | ALM_DIV144_ZERO | W0C | 0 | Asserted if the clkdiv144 in the CDRV_SER shift register is all zeros. |
| 0 | ALM_DIV160_ZERO | W0C | 0 | Asserted if the clkdiv160 in the CDRV_SER shift register is all zeros. |