ZHCSFU8B May 2016 – December 2021 ADC32RF80 , ADC32RF83
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SYSREF DEL[2:0] | 0 | 0 | 0 | 0 | 0 | ||
| W-0h | R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | SYSREF DEL2 | W | 0h | When the SYSREF delay feature is enabled (3Ch, bit 6) the delay can be adjusted in 25-ps steps; the first step is 175 ps. The PVT variation of each 25-ps step is ±10 ps. The 175-ps step is ±50 ps; see Table 8-43. |
| 6 | SYSREF DEL1 | R/W | ||
| 5 | SYSREF DEL0 | W | ||
| 4-0 | 0 | W | 0h | Must write 0 |
| STEP | SETTING | STEP (NOM) | TOTAL DELAY (NOM) |
|---|---|---|---|
| 1 | 01000 | 175 ps | 175 ps |
| 2 | 00111 | 25 ps | 200 ps |
| 3 | 00110 | 25 ps | 225 ps |
| 4 | 00101 | 25 ps | 250 ps |
| 5 | 00100 | 25 ps | 275 ps |
| 6 | 00011 | 25 ps | 300 ps |